[PDF][PDF] Efficient Implementation of 2-Bit Magnitude Comparator Using PTL

S Bhuvaneswari, R Prabakaran… - International Journal of …, 2017 - academia.edu
Nowadays the requirements of low power electronics play a vital role in various fields. In this
paper we introducing the novel comparator is one of the fundamental units in VLSI design …

[PDF][PDF] Low Power High Speed 3-2 Compressor

S Kumar, M Kumar - International Journal of Electrical, Electronics and …, 2013 - ijeemc.com
This paper describes a new design of low power 3-2 compressor circuit for high speed
multipliers. Power consumption of proposed 3-2 compressor circuit varies from 0.355 nW to …

Signal aware energy efficient approach for low power full adder design with adiabatic logic

D Kumar, M Kumar - Microsystem Technologies, 2022 - Springer
Prolonged battery life is the major concern for modern low power electronic devices.
Concentrating on this issue, in this paper a new structure of full adder has been proposed …

A High Speed and Low Power 8 Bit× 8 Bit Multiplier Design Using Novel Two Transistor (2T) XOR Gates

H Upadhyay, SR Chowdhury - Journal of Low Power …, 2015 - ingentaconnect.com
The paper proposes a novel design of two transistor (2T) XOR gate and its application to
design an 8 bit× 8 bit multiplier. The design explores the essence of suitably biasing the …

Design and Evaluation of Low Power 2 to 4 Decoder Circuit Using Three and Four Transistors NAND Gates

MK Channi, M Kumar - 2024 International Conference on …, 2024 - ieeexplore.ieee.org
This paper presents a new design of a 2 to 4 decoder constructed using 3-transistor NAND
gates, contrasting it with the conventional 4 transistor NAND gate-based technique. The …

[PDF][PDF] A body bias technique for low power full adder using XOR gate and pseudo NMOS transistor

P Pritty, M Kumar, M Zunairah - International Journal of …, 2019 - pdfs.semanticscholar.org
Power dissipation is a major issue in digital circuit design. As technology into developed into
range, power and delay becomes vital nanometer parameters to ameliorate the performance …

Design of an Energy-Efficient Parity Function Circuit

JB Kim - 2023 International Conference on Engineering and …, 2023 - ieeexplore.ieee.org
In this paper, we introduce an energy-efficient parity function circuit that is implemented
using XOR (exclusive-OR) and XNOR (exclusive-NOR) circuits. The proposed circuit …

Design of CMOS based D flip-flop with different low power techniques

A Bhardwaj, V Chauhan… - 2019 6th International …, 2019 - ieeexplore.ieee.org
This paper shows designs of CMOS based D flip flop circuits using the forced nMOS
stacking, LCNT (leakage controlled nMOS transistor), and LECTOR (leakage controlled …

Low power area efficient ALU with low power full adder

S Usha, M Rajendiran, A Kavitha - 2016 3rd International …, 2016 - ieeexplore.ieee.org
This paper presents a low Power Area efficient ALU using XNOR logic. The 4bit ALU design
is compared with various ALU implementation models with respect to their power …

[PDF][PDF] Comparative study on transistor based full adder designs

R Anitha - World Scientific News, 2016 - bibliotekanauki.pl
Recently in the generic systems the load on the processor is much heavy. The ability and the
challenging process have ended with larger core operations are in the core processor. This …