In-memory Computing based on Two Anti-Parallel Bipolar Memristors for Beyond von-Neumann Architecture

박태균 - 2022 - s-space.snu.ac.kr
As technologies for artificial intelligence, big data, and the internet of things have been
developing, the demand for the data-centric computation paradigm is increasing. The …

Design and Implemetation of Combinational Logic Circuits using Open Source Tool

N Divya, G Ilakkiya, M Dheeraj… - 2022 International …, 2022 - ieeexplore.ieee.org
Digital Systems plays an important role in today's modern technology. The practical
implementation of digital circuits in laboratories leads to a complex wired circuits and testing …

Performance analysis of 1-bit full adder using different design techniques

P Sreelatha, PK Lakshmi, R Rao - 2017 2nd IEEE International …, 2017 - ieeexplore.ieee.org
A fast and power-efficient full Adder plays key role in electronics trade especially performing
arithmetic operations in microprocessors, digital signal processing (DSP) and image …

32 bit power efficient carry select adder using 4T XNOR gate

SB Rashmi, V Oli - … on Applied and Theoretical Computing and …, 2016 - ieeexplore.ieee.org
Adders are the basic elements used in complex data processing for efficient VLSI design.
The CSLA adder circuit is used for the design of high speed processors. There is scope for …

[PDF][PDF] Low Power 4-2 Compressor for Arithmetic Circuits

R Garg, S Nehra, BP Singh - International Journal of Recent Technology …, 2013 - Citeseer
Most of the VLSI circuits used adders as a crucial portion, since they form the base element
of all arithmetic functions. Increasing demand for portable equipments requires area and …

Implementation and comparison of Boolean logic for different Nano Scaling technologies

GV Ganesh, M Raavi - 2021 5th International Conference on …, 2021 - ieeexplore.ieee.org
We have designed logic of (A+ B) C'in this paper using CMOS, DOMINO and Pass transistor
logic gates at different Nano scaling technologies. For any low power VLSI design, when …

[PDF][PDF] A New Design of Full Adder based on XNOR-XOR Circuit

R Garg, S Nehra, BP Singh - International Journal of Computer …, 2013 - Citeseer
This paper presents pre-layout simulations of a proposed 8T full adder design using a
proposed 3T XNOR gate cell. The proposed design remarkably reduces power consumption …

Low Power and Improved Speed Montgomery Multiplier using Universal Building Blocks

P Velrajkumar, C Senthilpari… - International Journal of …, 2019 - yadda.icm.edu.pl
Montgomery Multiplier (MM), which reduces complexity, gives lower power dissipation and
higher operating frequency. The main objective in designing these arithmetic blocks is to …

Low Power Adder Circuit Based on Coupling Technique

A Roy, A Sharma, A Mehra, SK Rajput - Intelligent Communication, Control …, 2018 - Springer
Today's technology is continuously scaling itself, thereby resulting in increasing density of
the transistors leading to high power dissipation on the chip. Therefore, we need to reduce …

A FPGA Implementation of Hard Systematic Error Correcting codes based Matching of Data Encoded Architecture with Low-Complexity, Low-Latency

SB Shirol, S Ramakrishnan… - 2018 Second …, 2018 - ieeexplore.ieee.org
Nowadays to get error free data is toughest task. To verify whether the data is error free or
not and decrease overall area and latency the new architecture has been designed which …