[PDF][PDF] Design and Implementation of Complex Multiplier Using Compressors

SM Sadiq, P Prathap, M Tech - International Journal & Magazine of … - academia.edu
In this paper, a low-power high speed Complex Multiplier using compressor circuit is
proposed for fast digital arithmetic integrated circuits. The compressor has been widely …

[PDF][PDF] An Efficient LSI Implementation of the Summation of Products in Convolution Operation for Binarized Neural Networks

M Takahashi, K Ito - sasimi.jp
Various applications of machine learning with convolutional neural networks (CNN) are
emerging. A binarized NN (BNN) is a CNN where the number of bits of input, activation, and …

[PDF][PDF] Power Efficient Shift Register Using Leakage

DM Ravi, KRV Lakshmi, LPG Bhavani, PS Satya - view.edu.in
VLSI is a stream of electronics engineering which involves putting millions and billions of
transistors logically together on to a single chip. VLSI circuits play a vital role in modern …

Design of low power split path Data Driven Dynamic ripple carry adders

M Kumar - 2014 International Conference on Computing for …, 2014 - ieeexplore.ieee.org
Addition is the fundamental operation used in computer arithmetic circuits and CMOS adder
is the basic component of these systems. This paper presents the designs of new 4-bit and 8 …

[PDF][PDF] Design and Simulation of a New Optimized Full-Adder Using Carbon Nano Tube Technology

AA Aghbolaghi, M Emadi - academia.edu
The full adder circuit is one of the most significant and prominent fundamental parts in digital
processors and integrated circuits since it can be used for implementing all four basic …

[PDF][PDF] Implementation of effective transistor level Hamming code circuit

P Bharadwaja, N Koppala, MV Naresh - academia.edu
Hamming codes are very simple error detecting codes. EXOR and AND gates are required
to implement hamming codes. Two input EXOR gate requires 12 transistors and two input …

[PDF][PDF] Low Power Full Adder Cells for Low Voltage and High Speed Applications

MG Priya - International Journal of Applied Engineering Research - researchgate.net
Fundamental building blocks of majority of the arithmetic and logic circuits are produced by
XNOR-XOR logic gates. This paper proposes a new 3T (three transistors) XNOR gate and …

[PDF][PDF] Power Efficient 14T Full Adder with Body Biasing Technique

S Singh, S Akashe - ijmemr.org
Leakage power reduction is the major issue in digital circuits. Many techniques are applied
to reduce leakage power. In this paper one such technique Body Biasing is used to design …

[PDF][PDF] A Novel Multi-Threshold CMOS Based 64-Bit Adder Design in 45nm CMOS Technology for Low Power Application

R Rastogi, S Pandey - ijssst.info
A new 64-bit low power MTCMOS XOR/XNOR based adder has been proposed in this
paper. The adder circuits have been designed in 45 nm Multi-threshold CMOS (MTCMOS) …

[PDF][PDF] Design and Analysis of Energy Efficient High-Speed Adders and Multipliers for Digital Signal Processors

KN Dungavath - 2017 - dspace.pondiuni.edu.in
The main objective of this research is to investigate the implementation and performance
analysis of efficient high-speed Adders and low-power Multipliers with compact design and …