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S Bhuvaneswari, R Prabakaran

[引用][C] Layout designing of full adder with minimum number of transistors using 32nm CMOS technology

R Rani

[引用][C] Design of High Performance Split Path Data Driven Dynamic Full Adders

MK Arun

[引用][C] Comparison of Single Bit 14T and 8T Full Adder for Low-Power VLSI Design

S Singh, S Narwal - technology, 2013