[图书][B] System test and diagnosis

WR Simpson, JW Sheppard - 2012 - books.google.com
System Test and Diagnosis is the first book on test and diagnosis at the system level,
defined as any aggregation of related elements that together form an entity of sufficient …

Selectively accessing test access ports in a multiple test access port environment

LD Whetsel - US Patent 6,073,254, 2000 - Google Patents
US6073254A - Selectively accessing test access ports in a multiple test access port
environment - Google Patents US6073254A - Selectively accessing test access ports in a …

Accumulator based deterministic BIST

R Dorsch, HJ Wunderlich - Proceedings International Test …, 1998 - ieeexplore.ieee.org
Most built-in self test (BIST) solutions require specialized test pattern generation hardware
which may introduce significant area overhead and performance degradation. Recently …

Design for testability in hardware software systems

HP Vranken, MF Witteman… - IEEE Design & Test of …, 1996 - ieeexplore.ieee.org
Design for testability in hardware-software systems - IEEE Design & Test of Computers Page 1
Design for Testability in Ha rdwa re-Softwa re Sys tern s CREATING TESTABLE designs is key …

Selecting different 1149.1 TAP domains from update-IR state

LD Whetsel, BS Haroun, BJ Lasher, A Kinra - US Patent 7,058,862, 2006 - Google Patents
Abstract IEEE 1149.1 Test Access Ports (TAPs) may be utilized at both IC and intellectual
property core design levels. TAPs serve as serial communication ports for accessing a …

[PDF][PDF] Testing framework-based software product lines

R Kauppinen - Master's Thesis, University of Helsinki, Department of …, 2003 - cs.helsinki.fi
A software product line can be seen as a process that can be used to implement a set of
software products that share common features [Nor01]. The resulting set of software …

Design for testability strategies for mixed signal & analogue designs-from layout to system

A Richardson, A Lechner… - 1998 IEEE International …, 1998 - ieeexplore.ieee.org
The cost and complexity of mixed signal and analogue production test programs is lending
to considerable interest in Design for testability (DfT) techniques that have the potential to …

Design-for-test strategies for analogue and mixed-signal integrated circuits

A Richardson, T Olbrich, V Liberali… - … Symposium on Circuits …, 1995 - ieeexplore.ieee.org
Recent advances in technology are leading to increases in the complexity and applications
of analogue and mixed-signal integrated circuits. This trend has been accompanied by an …

Roadmap for extending IEEE 1149.1 for hierarchical control of locally-stored, standardized command set, test programs

J Andrews - Proceedings., International Test Conference, 1995 - ieeexplore.ieee.org
This paper proposes a roadmap for an embedded system test strategy that uses IEEE
Standard 1149.1 as a multidrop, addressable backplane test bus to provide test access by a …

Identifying Intermittent Faults to Restrain BIT False Alarm based on EMD and HMM

Z Shen, C Huang, J Zhang… - 2020 35th Youth Academic …, 2020 - ieeexplore.ieee.org
An intermittent fault identification approach based on empirical mode decomposition (EMD)
and hidden Markov model (HMM) to restrain false alarm for built-in test (BIT) caused by …