Codex: Stochastic encoding method to relax resistive crossbar accelerator design requirements

T Liu, A Amirsoleimani, J Xu, F Alibart… - … on Circuits and …, 2022 - ieeexplore.ieee.org
A stochastic input encoding scheme (CODEX) is presented that aims to relax the analog-to-
digital converter (ADC) design requirements in memristor crossbar systems. CODEX …

Accelerating deep neural networks with analog memory devices

S Ambrogio, P Narayanan, H Tsai… - 2020 2nd IEEE …, 2020 - ieeexplore.ieee.org
Acceleration of training and inference of Deep Neural Networks (DNNs) with non-volatile
memory (NVM) arrays, such as Phase-Change Memory (PCM), shows promising …

Synapse cell optimization and back-propagation algorithm implementation in a domain wall synapse based crossbar neural network for scalable on-chip learning

D Kaushik, J Sharda, D Bhowmik - Nanotechnology, 2020 - iopscience.iop.org
On-chip learning in spin orbit torque driven domain wall synapse based crossbar fully
connected neural network (FCNN) has been shown to be extremely efficient in terms of …

Design of Analog-AI Hardware Accelerators for Transformer-based Language Models

GW Burr, H Tsai, W Simon, I Boybat… - 2023 International …, 2023 - ieeexplore.ieee.org
Analog Non-Volatile Memory-based accelerators offer high-throughput and energy-efficient
Multiply-Accumulate operations for the large Fully-Connected layers that dominate …

Low power neural network by reducing SRAM operating voltage

K Kozu, Y Tanabe, M Kitakami, K Namba - IEEE Access, 2022 - ieeexplore.ieee.org
With advancements in machine learning technology, networks are becoming increasingly
complex, and the extent of the computation involved is increasing. Consequently, the …

On-chip learning in a conventional silicon MOSFET based analog hardware neural network

N Dey, J Sharda, U Saxena, D Kaushik… - … Circuits and Systems …, 2019 - ieeexplore.ieee.org
Analog hardware Neural Network (NN) that uses a crossbar array of synapses to store the
weights of the NN provides an extremely fast and energy efficient hardware platform to …

[PDF][PDF] Design of Fully Analogue Artificial Neural Network with Learning Based on Backpropagation.

F Paulu, J Hospodka - Radioengineering, 2021 - pdfs.semanticscholar.org
A fully analogue implementation of training algorithms would speed up the training of
artificial neural networks. A common choice for training the feedforward networks is the …

The role of analog signal processing in upcoming telecommunication systems: Concept, challenges, and outlook

MM Safari, J Pourrostam - Signal Processing, 2024 - Elsevier
With the increasing demands in modern communications, the concepts of energy-efficient
and low-cost processors have received a lot of attention from researchers in recent years …

High‐speed adaptive analog filter based on fully analog artificial neural network

F Paulů, J Hospodka - International Journal of Circuit Theory …, 2023 - Wiley Online Library
This paper presents an innovative concept of a high‐speed and higher order adaptive filter.
A fully analog artificial neural network handles the adaption by using a filter bank for filtering …

NOR-type 3-D synapse array architecture based on charge-trap flash memory

JN Kim, J Lee, JE Kim, SW Hong… - IEEE Journal of the …, 2022 - ieeexplore.ieee.org
In this work, we proposed a three-dimensional (3-D) channel stacked array architecture
based on charge-trap flash (CTF) memory for an artificial neural network accelerator. The …