The next generation of multiprocessor system on chip (MPSoC) and chip multiprocessors
(CMPs) will contain hundreds or thousands of cores. Such a many‐core system requires …

Abstract NoCs (Network on Chips) are the most popular interconnection mechanism used
for systems that require flexibility, extensibility and low power consumption. However …

With the emergence of many-core architectures, it is quite likely that multiple applications will
run concurrently on a system. Existing locally and globally adaptive routing algorithms …

Efficient and deadlock-free routing is critical to the performance of networks-on-chip. The
effectiveness of any adaptive routing algorithm strongly depends on the underlying selection …

In this paper, we present a novel fully adaptive and fault-tolerant routing algorithm for
Network-on-Chips (NoCs) called Force-Directed Wormhole Routing (FDWR). The proposed …

As modern CMPs scale to ever increasing core counts, Networks-on-Chip (NoCs) are
emerging as an interconnection fabric, enabling communication between components …

The occurrence of congestion in on-chip networks can severely degrade the performance
due to increased message latency. In mesh topology, minimal methods can propagate …

In this paper, we propose a covert threat model for MPSoCs designed using 3rd party
Network-on-Chips (NoC). We illustrate that a malicious NoC can disrupt the availability of on …

Routing algorithms for networks-on-chip (NoCs) typically only have a small number of virtual
channels (VCs) at their disposal. Limited VCs pose several challenges to the design of fully …

In this paper, an adaptive routing algorithm for two-dimensional mesh network-on-chips
(NoCs) is presented. The algorithm, which is based on Dynamic XY (DyXY), is called …