3D-TemPo: Optimizing 3D DRAM Performance Under Temperature and Power Constraints
3D DRAM provides a significant performance boost resulting from substantial memory
bandwidth. However, the stacked memory architecture exhibits high power density, causing …
bandwidth. However, the stacked memory architecture exhibits high power density, causing …
Design and testing strategies for modular 3-D-multiprocessor systems using die-level through silicon via technology
G Beanato, P Giovannini, A Cevrero… - IEEE Journal on …, 2012 - ieeexplore.ieee.org
An innovative modular 3-D stacked multi-processor architecture is presented. The platform is
composed of completely identical stacked dies connected together by through-silicon-vias …
composed of completely identical stacked dies connected together by through-silicon-vias …
Analysis and mapping for thermal and energy efficiency of 3-D video processing on 3-D multicore processors
Three-dimensional video processing has high computation requirements and multicore
processors realized in 3-D integrated circuits (ICs) provide promising high performance …
processors realized in 3-D integrated circuits (ICs) provide promising high performance …
3D NOC for many-core processors
With an increasing number of processors forming many-core chip multiprocessors (CMP),
there exists a need for easily scalable, high-performance and low-power intra-chip …
there exists a need for easily scalable, high-performance and low-power intra-chip …
HRC: A 3D NoC architecture with genuine support for runtime thermal-aware task management
In spite of escalating thermal challenges imposed by high power consumption, most
reported 3D Network-on-chip (NoC) systems that adopt classic 3D cube (mesh) topology are …
reported 3D Network-on-chip (NoC) systems that adopt classic 3D cube (mesh) topology are …
基于三维芯片热驱动的扫描测试策略
神克乐， 向东 - 电子学报, 2013 - ejournal.org.cn
本文针对三维芯片测试, 首先提出了一种扫描结构, 这种结构考虑了硅通孔(through silicon vias)
互连的代价, 在有效的降低测试时间的同时, 还可以压缩测试激励数据和测试响应; …
互连的代价, 在有效的降低测试时间的同时, 还可以压缩测试激励数据和测试响应; …
ACO-based thermal-aware thread-to-core mapping for dark-silicon-constrained CMPs
The limitation on thermal budget in chip multiprocessor (CMP) results in a fraction of inactive
silicon regions called dark silicon, which significantly impacts the system performance. In …
silicon regions called dark silicon, which significantly impacts the system performance. In …
A bio-inspired hybrid thermal management approach for 3-D network-on-chip systems
3-D network-on-chip (NoC) systems are getting popular among the integrated circuit (IC)
manufacturer because of reduced latency, heterogeneous integration of technologies on a …
manufacturer because of reduced latency, heterogeneous integration of technologies on a …
Thermal-aware task scheduling for 3D-network-on-chip: A bottom to top scheme
Three-dimensional network-on-chip (3D-NoC) emerges as a potential multi-core
architecture delivering high performance, high energy efficiency and great scalability …
architecture delivering high performance, high energy efficiency and great scalability …
Fuzzy-based thermal management scheme for 3D chip multicores with stacked caches
L Shen, N Wu, G Yan - Electronics, 2020 - mdpi.com
By using through-silicon-vias (TSV), three dimension integration technology can stack large
memory on the top of cores as a last-level on-chip cache (LLC) to reduce off-chip memory …
memory on the top of cores as a last-level on-chip cache (LLC) to reduce off-chip memory …