Cooling mechanisms in 3D ICs: Thermo-mechanical perspective
SG Kandlikar, D Kudithipudi… - 2011 International …, 2011 - ieeexplore.ieee.org
Three-dimensional (3D) integrated circuits (IC) impose several challenges in thermal
management. Stacking vertical layers significantly increases the heat dissipation per unit …
management. Stacking vertical layers significantly increases the heat dissipation per unit …
Dynamic thermal management of high heat flux devices using embedded solid-liquid phase change materials and solid state coolers
Dynamic operation and control is an essential tool for thermal management of a number of
next generation electronic devices that suffer from localized hotspots with large heat fluxes …
next generation electronic devices that suffer from localized hotspots with large heat fluxes …
Real-time constrained task scheduling in 3d chip multiprocessor to reduce peak temperature
Chip multiprocessor technique has been implemented in embedded systems due to the
tremendous computation requirements. Three dimension chip multiprocessor architecture …
tremendous computation requirements. Three dimension chip multiprocessor architecture …
Energy-and Temperature-aware Scheduling: From Theory to an Implementation on Intel Processor
Q Bashir, M Pivezhandi… - 2022 IEEE 24th Int Conf on …, 2022 - ieeexplore.ieee.org
Temperature, energy, and performance are the key considerations of real-time multicore
systems. Thermal hotspots and high temperatures not only degrade reliability and per …
systems. Thermal hotspots and high temperatures not only degrade reliability and per …
Thermal-aware task allocation, memory mapping, and task scheduling for 3D stacked memory and processor architecture
WK Cheng, TW Hsu - IEEE 2013 Tencon-Spring, 2013 - ieeexplore.ieee.org
Heterogeneous integration enabled by 3D technology is one of the innovations for future
microprocessor design. By the heterogeneous integration of memory and multi-core …
microprocessor design. By the heterogeneous integration of memory and multi-core …
Design of a Sensitivity-Improved On-Chip Temperature Sensor Based on Inverse-Widlar Architecture
In this paper, a sensitivity-improved on-chip temperature sensor is designed and
demonstrated for heavy workload and fast processors. The temperature sensor is based on …
demonstrated for heavy workload and fast processors. The temperature sensor is based on …
On optimizing system energy of voltage–frequency island based 3-D multi-core SoCs under thermal constraints
S Jin, Y Wang, T Liu - Integration, 2015 - Elsevier
Abstract Three dimensional (3-D) multi-core SoC has been recognized as a promising
solution for implementing complex applications with lower system energy. Recently, voltage …
solution for implementing complex applications with lower system energy. Recently, voltage …
Dynamic temperature aware scheduling for CPU-GPU 3D multicore processor with regression predictor
The 3D stacked integration of CPU, GPU and DRAM dies is a rising horizon in chip
fabrication, where dies are vertically interconnected by TSVs (Through-Silicon Vias) to …
fabrication, where dies are vertically interconnected by TSVs (Through-Silicon Vias) to …
Optimal sprinting pattern in thermal constrained CMPs
J Wang, Z Chen, S Guo, Y Li… - IEEE Transactions on …, 2019 - ieeexplore.ieee.org
As studied in literatures, Computational Sprinting (CS) is a promising technique to tackle the
thermal challenge for Chip Multi-Processors (CMPs) in dark silicon era. Sprinting pattern, the …
thermal challenge for Chip Multi-Processors (CMPs) in dark silicon era. Sprinting pattern, the …
Algorithms for the thermal scheduling problem
K Mukherjee, S Khuller… - 2013 IEEE 27th …, 2013 - ieeexplore.ieee.org
The energy costs for cooling a data center constitute a significant portion of the overall
running costs. Thermal imbalance and hot spots that arise due to imbalanced workloads …
running costs. Thermal imbalance and hot spots that arise due to imbalanced workloads …