Interconnect structure for semiconductor devices
HL Chang, HC Tsai, YC Lu, SM Jang - US Patent 9,219,036, 2015 - Google Patents
A method of manufacturing a semiconductor device with a cap layer for a copper
interconnect structure formed in a dielectric layer is provided. In an embodiment, a …
interconnect structure formed in a dielectric layer is provided. In an embodiment, a …
Integrating PECVD low-k dielectric layers.(Deposition)
J Sabharwal, P Lee, D Sugiarto, T Sato, N Oka… - Solid State …, 2002 - go.gale.com
PECVD-deposited SiOC films are leading candidates to replace CVD [SiO. sub. 2] and
fluorinated [SiO. sub. 2] as lower-k interlayer dielectrics in multilevel interconnects [1, 2] …
fluorinated [SiO. sub. 2] as lower-k interlayer dielectrics in multilevel interconnects [1, 2] …
[引用][C] 표면처리를통한Cu 도선과SiCN 캡핑층간의접합신뢰성최적화
김동준， 강수민， 이선우， 이인화， 박승주… - 대한기계학회춘추학술 …, 2022 - dbpia.co.kr
Adhesion and mechanical reliability enhancement are highly demanded in memory devices
due to delamination issues between Cu/SiCN capping layer. The Cu surface tends to be …
due to delamination issues between Cu/SiCN capping layer. The Cu surface tends to be …
[引用][C] Post CMP passivation of copper interconnects
[引用][C] Interface Reliability of High Performance Interconnects (Invited) C. Goldberg, M. Freeman', S. Kirksey', D. Sieloff', S. Filipiak', L. Mercado², G. Braeckelmann'KH …
C Goldberg - … 2002 (AMC 2002): Proceedings of the …, 2003 - Materials Research Society