Comprehensive study of 1-bit full adder cells: review, performance comparison and scalability analysis
Full Adder (FA) circuits are integral components in the design of Arithmetic Logic Units
(ALUs) of modern computing systems. Recently, there have been massive research interests …
(ALUs) of modern computing systems. Recently, there have been massive research interests …
Performance analysis of a low-power high-speed hybrid 1-bit full adder circuit
P Bhattacharyya, B Kundu, S Ghosh… - … Transactions on very …, 2014 - ieeexplore.ieee.org
In this paper, a hybrid 1-bit full adder design employing both complementary metal–oxide–
semiconductor (CMOS) logic and transmission gate logic is reported. The design was first …
semiconductor (CMOS) logic and transmission gate logic is reported. The design was first …
Low-power and fast full adder by exploring new XOR and XNOR gates
H Naseri, S Timarchi - IEEE transactions on very large scale …, 2018 - ieeexplore.ieee.org
In this paper, novel circuits for XOR/XNOR and simultaneous XOR-XNOR functions are
proposed. The proposed circuits are highly optimized in terms of the power consumption …
proposed. The proposed circuits are highly optimized in terms of the power consumption …
Design of a scalable low-power 1-bit hybrid full adder for fast computation
A novel design of a hybrid Full Adder (FA) using Pass Transistors (PTs), Transmission Gates
(TGs) and Conventional Complementary Metal Oxide Semiconductor (CCMOS) logic is …
(TGs) and Conventional Complementary Metal Oxide Semiconductor (CCMOS) logic is …
Design and implementation of 20-T hybrid full adder for high-performance arithmetic applications
Most of the full adder (FA) circuits are implemented through a hybrid logic style using three
different modules. The principal peculiarity of these hybrid logic style-based FA cells is that …
different modules. The principal peculiarity of these hybrid logic style-based FA cells is that …
A novel hybrid full adder based on gate diffusion input technique, transmission gate and static CMOS logic
This research proposes a hybrid Full Adder (FA) cell using a combination of Gate Diffusion
Input (GDI) technique, Transmission Gate (TG) and conventional Static CMOS (C-CMOS) …
Input (GDI) technique, Transmission Gate (TG) and conventional Static CMOS (C-CMOS) …
Ultra‐low‐voltage GDI‐based hybrid full adder design for area and energy‐efficient computing systems
K Sanapala, R Sakthivel - IET Circuits, Devices & Systems, 2019 - Wiley Online Library
In recent years, ultra‐low‐voltage (ULV) operation is gaining more importance for achieving
minimum energy consumption. Full adder is the basic computational arithmetic block in …
minimum energy consumption. Full adder is the basic computational arithmetic block in …
1-Bit FinFET carry cells for low voltage high-speed digital signal processing applications
CS Pittala, V Vijay, BNK Reddy - Silicon, 2023 - Springer
In this paper, new high speed and low voltage 1-bit FinFET full adder carry cells are
proposed for multi-bit arithmetic applications used in Digital Signal Processing (DSP) …
proposed for multi-bit arithmetic applications used in Digital Signal Processing (DSP) …
Overview and comparative performance analysis of various full adder cells in 90 nm technology
Full Adders considered as the major component in Arithmetic Logic Unit of digital signal
processing chips and microprocessors gained much interest among researchers over the …
processing chips and microprocessors gained much interest among researchers over the …
High-performance 1-bit full adder with excellent driving capability for multistage structures
In this letter, a low-power 1-bit full-adder (FA) cell is proposed based on the transmission
gate (TG) to attain a special module for generating full-swing Carry output. The cell benefits …
gate (TG) to attain a special module for generating full-swing Carry output. The cell benefits …