ECM: Effective capacity maximizer for high-performance compressed caching

S Baek, HG Lee, C Nicopoulos, J Lee… - 2013 IEEE 19th …, 2013 - ieeexplore.ieee.org
Compressed Last-Level Cache (LLC) architectures have been proposed to enhance system
performance by efficiently increasing the effective capacity of the cache, without physically …

Exploring the potential for collaborative data compression and hard-error tolerance in pcm memories

A Jadidi, M Arjomand, MK Tavana… - 2017 47th Annual …, 2017 - ieeexplore.ieee.org
Limited write endurance is the main obstacle standing in the way of using phase change
memory (PCM) in future computing systems. While several wear-leveling and hard-error …

Building energy-efficient multi-level cell STT-RAM caches with data compression

L Liu, P Chi, S Li, Y Cheng, Y Xie - 2017 22nd Asia and South …, 2017 - ieeexplore.ieee.org
Spin-transfer torque magnetic random access memory (STT-RAM) technology has emerged
as a potential replacement of SRAM in cache design, especially for building large-scale and …

Power protocol: reducing power dissipation on off-chip data buses

K Basu, A Choudhary, J Pisharath… - 35th Annual IEEE …, 2002 - ieeexplore.ieee.org
Power consumption is becoming increasingly important for both embedded and high-
performance systems. Off-chip data buses can be a major power consumer. In this paper we …

Distilling the essence of raw video to reduce memory usage and energy at edge devices

H Zhang, S Zhao, A Pattnaik, MT Kandemir… - Proceedings of the …, 2019 - dl.acm.org
Video broadcast and streaming are among the most widely used applications for edge
devices. Roughly 82% of the mobile internet traffic is made up of video data. This is likely to …

Toggle-aware compression for GPUs

G Pekhimenko, E Bolotin, M O'Connor… - IEEE Computer …, 2015 - ieeexplore.ieee.org
Memory bandwidth compression can be an effective way to achieve higher system
performance and energy efficiency in modern data-intensive applications by exploiting …

Could compression be of general use? evaluating memory compression across domains

S Sardashti, DA Wood - ACM Transactions on Architecture and Code …, 2017 - dl.acm.org
Recent proposals present compression as a cost-effective technique to increase cache and
memory capacity and bandwidth. While these proposals show potentials of compression …

A block-level log-block management scheme for MLC NAND flash memory storage systems

Y Guan, G Wang, C Ma, R Chen… - IEEE Transactions on …, 2017 - ieeexplore.ieee.org
NAND flash memory is the major storage media for both mobile storage cards and
enterprise Solid-State Drives (SSDs). Log-block-based Flash Translation Layer (FTL) …

Frequent value compression in packet-based NoC architectures

P Zhou, B Zhao, Y Du, Y Xu, Y Zhang… - 2009 Asia and South …, 2009 - ieeexplore.ieee.org
The proliferation of chip multiprocessors (CMPs) has led to the integration of large on-chip
caches. For scalability reasons, a large on-chip cache is often divided into smaller banks …

Parity++: Lightweight error correction for last level caches

I Alam, C Schoeny, L Dolecek… - 2018 48th Annual IEEE …, 2018 - ieeexplore.ieee.org
As the size of on-chip SRAM caches is increasing rapidly and the physical dimension of the
SRAM devices is decreasing, reliability of caches is becoming a growing concern. This is …