Larger cache sizes closer to processor cores increase processing efficiency, but physical
limitations restrict cache sizes at a given latency. Effective cache capacity can be expanded …

A common way to protect data stored in DRAM and related memory systems is through the
use of an error-correcting code such as the extended Hamming code. Traditionally, these …

A practical way to increase the effective capacity of a microprocessor's cache, without
physically increasing the cache size, is to employ data compression. Last-Level Caches …

Current microprocessors spend a huge percentage of the die area to implement the memory
hierarchy. Moreover, cache memory is responsible for a significant percentage of the total …

Phase-Change Memory (PCM) is emerging as a promising new memory technology, due to
its inherent ability to scale deeply into the nanoscale regime. However, PCM is still marred …

This chapter contains sections titled: Introduction Motivation of Partial Cache Line
Prefetching Dynamic Value Representation Partial Cache Line Prefetching Cache Design …

Resource disaggregation offers a cost effective solution to resource scaling, utilization, and
failure-handling in data centers by physically separating hardware devices in a server …

Chip multiprocessors (CMP) are a convenient way of leveraging from the technological
trends to build high-end and embedded systems that are performance and power efficient …

Increasing cache latencies limit L1 cache sizes. In this paper we investigate restrictive
compression techniques for level 1 data cache, to avoid an increase in the cache access …

Chip multiprocessors (CMPs) combine multiple processors on a single die, typically with
private level-one caches and a shared level-two cache. The increasing number of …