Energy optimization for large-scale 3D manycores in the dark-silicon era

S Majzoub, RA Saleh, I Ashraf, M Taouil… - IEEE …, 2019 - ieeexplore.ieee.org
In this paper, we study the impact of the idle/dynamic power consumption ratio on the
effectiveness of a multi-V dd/frequency manycore design. We propose a new tool called …

Gate sizing

S Held, J Hu - Electronic Design Automation for IC Implementation …, 2017 - taylorfrancis.com
Further techniques for optimizing gate delays have a smaller impact on the end result
compared to sizing and Vt-assignment and are, therefore, seldom used. First, the ratio of the …

[引用][C] Design of A Low-power Processor for Internet of Things

OS Gwon, JH Oh, JK Kim, JW Shin, JW Lee, SE Lee