Ramulator: A fast and extensible DRAM simulator

Y Kim, W Yang, O Mutlu - IEEE Computer architecture letters, 2015 - ieeexplore.ieee.org
Recently, both industry and academia have proposed many different roadmaps for the future
of DRAM. Consequently, there is a growing need for an extensible DRAM simulator, which …

Rowpress: Amplifying read disturbance in modern dram chips

H Luo, A Olgun, AG Yağlıkçı, YC Tuğrul… - Proceedings of the 50th …, 2023 - dl.acm.org
Memory isolation is critical for system reliability, security, and safety. Unfortunately, read
disturbance can break memory isolation in modern DRAM chips. For example, RowHammer …

DAMOV: A new methodology and benchmark suite for evaluating data movement bottlenecks

GF Oliveira, J Gómez-Luna, L Orosa, S Ghose… - IEEE …, 2021 - ieeexplore.ieee.org
Data movement between the CPU and main memory is a first-order obstacle against improv
ing performance, scalability, and energy efficiency in modern systems. Computer systems …

Fine-grained DRAM: Energy-efficient DRAM for extreme bandwidth systems

M O'Connor, N Chatterjee, D Lee, J Wilson… - Proceedings of the 50th …, 2017 - dl.acm.org
Future GPUs and other high-performance throughput processors will require multiple TB/s of
bandwidth to DRAM. Satisfying this bandwidth demand within an acceptable energy budget …

Shadow: Preventing row hammer in dram with intra-subarray row shuffling

M Wi, J Park, S Ko, MJ Kim, NS Kim… - … Symposium on High …, 2023 - ieeexplore.ieee.org
As Row Hammer (RH) attacks have been a critical threat to computer systems, numerous
hardware-based (HWbased) RH mitigation strategies have been proposed. However, the …

Trim: Enhancing processor-memory interfaces with scalable tensor reduction in memory

J Park, B Kim, S Yun, E Lee, M Rhu… - MICRO-54: 54th Annual …, 2021 - dl.acm.org
Personalized recommendation systems are gaining significant traction due to their industrial
importance. An important building block of recommendation systems consists of the …

ELP2IM: Efficient and low power bitwise operation processing in DRAM

X Xin, Y Zhang, J Yang - 2020 IEEE International Symposium …, 2020 - ieeexplore.ieee.org
Recently proposed DRAM based memory-centric architectures have demonstrated their
great potentials in addressing the memory wall challenge of modern computing systems …

Mithril: Cooperative row hammer protection on commodity dram leveraging managed refresh

MJ Kim, J Park, Y Park, W Doh, N Kim… - … Symposium on High …, 2022 - ieeexplore.ieee.org
Since its public introduction in the mid-2010s, the Row Hammer (RH) phenomenon has
drawn significant attention from the research community due to its security implications …

Architecting an energy-efficient dram system for gpus

N Chatterjee, M O'Connor, D Lee… - … Symposium on High …, 2017 - ieeexplore.ieee.org
This paper proposes an energy-efficient, high-throughput DRAM architecture for GPUs and
throughput processors. In these systems, requests from thousands of concurrent threads …

Solar-DRAM: Reducing DRAM access latency by exploiting the variation in local bitlines

J Kim, M Patel, H Hassan… - 2018 IEEE 36th …, 2018 - ieeexplore.ieee.org
DRAM latency is a major bottleneck for many applications in modern computing systems. In
this work, we rigorously characterize the effects of reducing DRAM access latency on 282 …