Several graphics processing elements are interconnected in a ring using a plurality of
individual busses. Each bus interconnects a pair of the graphics processing elements and …

Abstract Systems and methods are disclosed for implementing and using data structures
comprised of a hierarchy of queues or linked list data structures. A queue or linked list …

OSSO Y.................. s virtual channels is created, the one or more Switches compris ing, for
each processor, a corresponding Switch in the one or more switches. The data is transmitted …

Abstract Systems and methods for scheduling data packets in a network processor are
disclosed. Embodiments provide a network processor that comprises a best-effort scheduler …

(57) ABSTRACT A mechanism is provided for collective acceleration unit tree flow control
forms a logical tree (sub-network) among those processors and transfers “collective'packets …

This application is a continuation of US. application Ser. No. 09/065,118,? led on Apr. 23,
1998 now US. Pat. No. 6,570,850; the disclosure of the prior application is consid ered part …

An interface circuit included in a ring interconnected group 21 Appl. No.: 08/846,831 of
processing elements includes a backup FIFO to tempo 22 Filed: May 1, 1997 rarily Store …

5,428,803 A 6/1995 Chen et al. 2003/0233388 A1 12/2003 Glasco et al. 3. A g XRdv et al
2004/0073831 A1* 4/2004 Yanai et al..................... 714/7 563,068 A 3, 1997 hy …

First worldwide family litigation filed litigation https://patents. darts-ip. com/? family=
24836235&utm_source= google_patent&utm_medium= platform_link&utm_campaign …

US6038217A - Rate shaping in per-flow output queued routing mechanisms for available bit rate
(ABR) service in networks having segmented ABR control loops - Google Patents US6038217A …