Time-wheel ATM cell scheduling

A Joffe, A Birger - US Patent 6,041,059, 2000 - Google Patents
US6041059A - Time-wheel ATM cell scheduling - Google Patents US6041059A - Time-wheel
ATM cell scheduling - Google Patents Time-wheel ATM cell scheduling Download PDF Info …

System for data processing using a multi-tiered full-graph interconnect architecture

LB Arimilli, RK Arimilli, R Rajamony… - US Patent …, 2012 - Google Patents
A system is provided for implementing a multi-tiered full-graph interconnect architecture. In
order to implement a multi-tiered full-graph interconnect architecture, a plurality of …

System and method for providing multiple redundant direct routes between supernodes of a multi-tiered full-graph interconnect architecture

LB Arimilli, RK Arimilli, R Rajamony - US Patent 7,769,891, 2010 - Google Patents
5,613,068 A 3/1997 Gregg et al. 2004/O190517 A1 9/2004 Gupta et al. 5,629,928 A 5/1997
Calvignac et al. 2004/O193693 A1 9/2004 Gangwal et al. 5,701.416 A 12/1997 Thorson et …

Queue service interval based cell schedular with hierarchical queuing configurations

N Yin, M Borden, S Li, M Hluchyj - US Patent 6,810,012, 2004 - Google Patents
To determine when to service a cell queue in an ATM network, a cell scheduler can use an
ideal service interval time. The ideal service interval time of each cell queue is the reciprocal …

QoS scheduler and method for implementing quality of service with cached status array

WJ Goetzinger, GH Handlogten, JF Mikos… - US Patent …, 2006 - Google Patents
A QoS scheduler, scheduling method, and computer program product are provided for
implementing Quality-of-Service (QoS) scheduling with a cached status array. A plurality of …

System for providing a cluster-wide system clock in a multi-tiered full-graph interconnect architecture

LB Arimilli, RK Arimilli, BC Drerup, JB Joyner… - US Patent …, 2010 - Google Patents
5,602,839 A 2/1997 Annapareddy et al. 2003/017.4648 A1 9/2003 Wang et al. 5,613,068 A
3/1997 Gregg et al. 2003/0182614 A1 9, 2003 Schroeder 5,629,928 A 5/1997 Calvignac et …

Virtual path shaping

DW Carr, DLS Lee - US Patent 6,163,542, 2000 - Google Patents
An apparatus and a method for shaping ATM cell traffic emitted onto a virtual path
connection in an ATM network are described. Component virtual channel connections are …

Network processor having fast flow queue disable process

WJ Goetzinger, GH Handlogten, JF Mikos… - US Patent …, 2010 - Google Patents
6,041,059 A 3/2000 Joffe etal 7,058,974 Bl* 6/2006 Maher et a1................... 726/13
6,052,751 A 4/2000 Runaldue eta1~ 7,062,568 Bl* 6/2006 Senevirathne et a1........ 709/234 …

System and Method for Data Processing Using a Low-Cost Two-Tier Full-Graph Interconnect Architecture

LB Arimilli, RK Arimilli, R Rajamony… - US Patent App. 12 …, 2009 - Google Patents
(57) ABSTRACT A system and method are provided for implementing a two tier full-graph
interconnect architecture. In order to imple ment a two-tier full-graph interconnect …

Cell queuing in ATM switches

A Joffe, A Birger, P Mishra - US Patent 6,128,278, 2000 - Google Patents
In a network Switch, data received on an input connection can be transmitted on one or
more output connections. When the Switch receives a command to remove an output …