J Gurley, CE Moore, TJ Schlichter - US Patent 7,539,142, 2009 - Google Patents
A differential time domain digital communication bridge module interfaces 100 Mbps Ethernet traffic with a T3 communication link, using a relatively small sized data buffer. To …
A Joffe, D Vyshetsky - US Patent 7,590,785, 2009 - Google Patents
In a multi-tasking pipelined processor, consecutive instructions are executed by different tasks, eliminating the need to purge an instruction execution pipeline of subsequent …
WJ Goetzinger, GH Handlogten, JF Mikos… - US Patent …, 2007 - Google Patents
In a first aspect, a network processor includes a scheduler in which a scheduling queue is maintained. A last frame is dispatched from a flow queue maintained in the network …
H Kosugi, P Hamilton - US Patent 5,867,664, 1999 - Google Patents
In a parallel processor system, a plurality of nodes each comprising a processor and a main storage unit are interconnected through a network, wherein a user process is executed …
WJ Goetzinger, GH Handlogten, JF Mikos… - US Patent …, 2007 - Google Patents
A scheduler for a network processor includes a scheduling queue in which weighted fair queuing is applied to define a sequence in which flows are to be serviced. The scheduling …
M Hayashi - US Patent 5,802,059, 1998 - Google Patents
In a communication system, isochronous data can be continuously received without any interruption, and also asynchronous data irregularly transmitted can be received without loss …
RR Faget, RD Larson, BA Alcorn - US Patent 5,907,691, 1999 - Google Patents
According to one embodiment of the invention, an inter facing circuit includes an input Storage element, an output Storage element, a non-priority interface output Storage …
WJ Goetzinger, GH Handlogten, JF Mikos… - US Patent …, 2011 - Google Patents
A data communication apparatus includes a plurality of output ports and a scheduler for assigning priorities for outbound data frames. The scheduler includes one or more …