Over the past decade, the primary focus for improving the performance of nano-electronic
metal interconnect structures has been to reduce the impact of resistance-capacitance (RC) …

This paper reviews the mechanical and fracture properties of porous ultralow-k dielectrics
with the focus on chip package interaction related issues. It is shown that the mechanical …

This paper presents an in-depth overview of the application and impact of UV/VUV light in
advanced interconnect technology. UV light application in BEOL historically was mainly …

The active layers of perovskite solar cells are also structural layers and are central to
ensuring that the structural integrity of the device is maintained over its operational lifetime …

High-dielectric constant (high-k) gate oxides and low-dielectric constant (low-k) interlayer
dielectrics (ILD) have dominated the nanoelectronic materials research scene over the past …

Abstract Three-dimensional (3D) integration using the through-silicon via (TSV) approach
becomes one promising technology in 3D packaging. 2.5 D through-silicon interposer (TSI) …

Mechanical failures in low-k interlayer dielectrics and related interfaces during flip-chip-
packaging processes have raised serious reliability concerns. The problem can be traced to …

Due to the miniaturization of integrated circuits, their thermo-mechanical reliability tends to
become a truly critical design criterion. Especially the introduction of copper and low-k …

Numerical fatigue damage models can help to save cost and time when studying fatigue
damage in the copper metallization layers of power semiconductor devices. However, their …

Cu pillar technology can cater for high I/O, fine pitch, and miniaturization requirements
compared with wire bonding and conventional solder flip-chip technologies. However, chip …