A digital fractional-N PLL with a PVT and mismatch insensitive TDC utilizing equivalent time sampling technique

HS Kim, C Ornelas, K Chandrashekar… - IEEE journal of solid …, 2013 - ieeexplore.ieee.org
A 6-bit time-to-digital converter that achieves mismatch free operation by using a single
delay cell and sampling flip-flop is presented. The proposed TDC was integrated in a digital …
被引用次数：22 相关文章

[引用][C] A Digital Fractional-N PLL With a PVT and Mismatch Insensitive TDC Utilizing Equivalent Time Sampling Technique

HS KIM, C ORNELAS… - IEEE journal of solid …, 2013 - pascal-francis.inist.fr
A Digital Fractional-N PLL With a PVT and Mismatch Insensitive TDC Utilizing Equivalent
Time Sampling Technique CNRS Inist Pascal-Francis CNRS Pascal and Francis …

[引用][C] A Digital Fractional-N PLL With a PVT and Mismatch Insensitive TDC Utilizing Equivalent Time Sampling Technique

HS Kim, C Ornelas, K Chandrashekar… - IEEE Journal of …, 2013 - ui.adsabs.harvard.edu
A Digital Fractional-N PLL With a PVT and Mismatch Insensitive TDC Utilizing Equivalent Time
Sampling Technique - NASA/ADS Now on home page ads icon ads Enable full ADS view …

A Digital Fractional-N PLL With a PVT and Mismatch Insensitive TDC Utilizing Equivalent Time Sampling Technique

HS Kim, C Ornelas, K Chandrashekar, D Shi… - IEEE Journal of Solid …, 2013 - infona.pl
A 6-bit time-to-digital converter that achieves mismatch free operation by using a single
delay cell and sampling flip-flop is presented. The proposed TDC was integrated in a digital …

[引用][C] A Digital Fractional-N PLL With a PVT and Mismatch Insensitive TDC Utilizing Equivalent Time Sampling Technique

HS KIM, C ORNELAS… - … journal of solid …, 2013 - Institute of Electrical and Electronics …