Performance effects of pipeline architecture on an FPGA-based binary32 floating point multiplier

X Jiang, P Xiao, M Qiu, G Wang - Microprocessors and Microsystems, 2013 - Elsevier
High pipeline depth architecture with pipeline stage more than five is rarely adopted in
existing multipliers for real world applications. In this paper, a field programmable gate array …
被引用次数：16 相关文章

Performance effects of pipeline architecture on an FPGA-based binary32 floating point multiplier

X Jiang, P Xiao, M Qiu, G Wang - Microprocessors & Microsystems, 2013 - dl.acm.org
High pipeline depth architecture with pipeline stage more than five is rarely adopted in
existing multipliers for real world applications. In this paper, a field programmable gate array …

[引用][C] Performance effects of pipeline architecture on an FPGA-based binary32 floating point multiplier

X Jiang, P Xiao, M Qiu, G Wang - 2013 - corc.ac.cn
中国开放科研知识云: Performance effects of pipeline architecture on an FPGA-based binary32
floating point multiplier 验证码: 换一张 忘记密码? 记住我 取消 登录 CORC 首页 科研机构 检索 知识 …

Performance effects of pipeline architecture on an FPGA-based binary32 floating point multiplier

X Jiang, P Xiao, M Qiu, G Wang - Microprocessors and Microsystems, 2013 - infona.pl
High pipeline depth architecture with pipeline stage more than five is rarely adopted in
existing multipliers for real world applications. In this paper, a field programmable gate array …