HiRA: Hidden row activation for reducing refresh latency of off-the-shelf DRAM chips

AG Yağlikçi, A Olgun, M Patel, H Luo… - 2022 55th IEEE/ACM …, 2022 - ieeexplore.ieee.org
DRAM is the building block of modern main memory systems. DRAM cells must be
periodically refreshed to prevent data loss. Refresh operations degrade system performance …
被引用次数：42 相关文章

HiRA: Hidden Row Activation for Reducing Refresh Latency of Off-the-Shelf DRAM Chips

Y Giray, A Olgun, M Patel, H Luo… - Proceedings of the …, 2022 - 193.140.108.196
DRAM is the building block of modern main memory systems. DRAM cells must be
periodically refreshed to prevent data loss. Refresh operations degrade system performance …

HiRA: Hidden Row Activation for Reducing Refresh Latency of Off-the-Shelf DRAM Chips

Y Giray, A Olgun, M Patel, H Luo, H Hassan… - Proceedings of the …, 2022 - gcris.etu.edu.tr
DRAM is the building block of modern main memory systems. DRAM cells must be
periodically refreshed to prevent data loss. Refresh operations degrade system performance …

HiRA: Hidden Row Activation for Reducing Refresh Latency of Off-the-Shelf DRAM Chips

AG Yağlikçi, A Olgun, M Patel… - 2022 55th IEEE …, 2022 - research-collection.ethz.ch
DRAM is the building block of modern main memory systems. DRAM cells must be
periodically refreshed to prevent data loss. Refresh operations degrade system performance …

HiRA: Hidden Row Activation for Reducing Refresh Latency of Off-the-Shelf DRAM Chips

AG Yağlıkçı, A Olgun, M Patel, H Luo, H Hassan… - arXiv preprint arXiv …, 2022 - arxiv.org
DRAM is the building block of modern main memory systems. DRAM cells must be
periodically refreshed to prevent data loss. Refresh operations degrade system performance …

HiRA: Hidden Row Activation for Reducing Refresh Latency of Off-the-Shelf DRAM Chips

AG Yaglikci, A Olgun, M Patel, H Luo… - 2022 55th IEEE/ACM …, 2022 - computer.org
DRAM is the building block of modern main memory systems. DRAM cells must be
periodically refreshed to prevent data loss. Refresh operations degrade system performance …

HiRA: Hidden Row Activation for Reducing Refresh Latency of Off-the-Shelf DRAM Chips

AG Yağlıkçı, A Olgun, M Patel, H Luo… - Proceedings of the 55th …, 2022 - dl.acm.org
DRAM is the building block of modern main memory systems. DRAM cells must be
periodically refreshed to prevent data loss. Refresh operations degrade system performance …