Implementation of gating technique with modified scan flip-flop for low power testing of VLSI chips

R Jayagowri, KS Gurumurthy - Progress in VLSI Design and Test: 16th …, 2012 - Springer
We present a technique to reduce the power of combinational circuits during testing. Power
dissipation of IC during test mode is greater than the IC's normal mode of functioning. During …
被引用次数：3 相关文章

Implementation of Gating Technique with Modified Scan Flip-Flop for Low Power Testing of VLSI Chips

R Jayagowri, KS Gurumurthy - Progress in VLSI Design and Test …, 2012 - books.google.com
We present a technique to reduce the power of combinational circuits during testing. Power
dissipation of IC during test mode is greater than the IC's normal mode of functioning. During …

Implementation of Gating Technique with Modified Scan Flip-Flop for Low Power Testing of VLSI Chips

R Jayagowri, KS Gurumurthy - Progress in VLSI Design and Test, 2012 - Springer
We present a technique to reduce the power of combinational circuits during testing. Power
dissipation of IC during test mode is greater than the IC's normal mode of functioning. During …

Implementation of gating technique with modified scan flip-flop for low power testing of VLSI chips

R Jayagowri, KS Gurumurthy - … of the 16th international conference on …, 2012 - dl.acm.org
We present a technique to reduce the power of combinational circuits during testing. Power
dissipation of IC during test mode is greater than the IC's normal mode of functioning. During …

[引用][C] Implementation of Gating Technique with Modified Scan Flip-Flop for Low Power Testing of VLSI Chips

R Jayagowri, K Gurumurthy - Progress in VLSI Design and Test, 2012 - Springer