Patterning of narrow porous SiOCH trenches using a TiN hard mask

T Chevolleau, D Eon, R Bouyssou, B Pelissier… - Microelectronic …, 2008 - Elsevier
For the next technological generations of integrated circuits, the traditional challenges faced
by etch plasmas (profile control, selectivity, critical dimensions, uniformity, defects,…) …

Patterning of narrow porous SiOCH trenches using a TiN hard mask

M Darnon, T Chevolleau, D Eon, R Bouyssou… - Microelectronic …, 2008 - dl.acm.org
For the next technological generations of integrated circuits, the traditional challenges faced
by etch plasmas (profile control, selectivity, critical dimensions, uniformity, defects,...) …

[引用][C] Patterning of narrow porous SiOCH trenches using a TiN hard mask

M DARNON, T CHEVOLLEAU… - Microelectronic …, 2008 - pascal-francis.inist.fr
Patterning of narrow porous SiOCH trenches using a TiN hard mask CNRS Inist Pascal-Francis
CNRS Pascal and Francis Bibliographic Databases Simple search Advanced search Search …

Patterning of narrow porous SiOCH trenches using a TiN hard mask

M Darnon, T Chevolleau, D Eon… - Microelectronic …, 2008 - hal.univ-grenoble-alpes.fr
For the next technological generations of integrated circuits, the traditional challenges faced
by etch plasmas (profile control, selectivity, critical dimensions, uniformity, defects,…) …

Patterning of narrow porous SiOCH trenches using a TiN hard mask

M Darnon, T Chevolleau, D Eon, R Bouyssou… - Microelectronic …, 2008 - hal.science
For the next technological generations of integrated circuits, the traditional challenges faced
by etch plasmas (profile control, selectivity, critical dimensions, uniformity, defects,…) …

[引用][C] Patterning of narrow porous SiOCH trenches using a TiN hard mask

M Darnon, T Chevolleau, D Eon, R Bouyssou… - Microelectronic …, 2008 - cir.nii.ac.jp
Patterning of narrow porous SiOCH trenches using a TiN hard mask | CiNii Research CiNii
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Patterning of narrow porous SiOCH trenches using a TiN hard mask

M Darnon, T Chevolleau, D Eon, R Bouyssou… - Microelectronic …, 2008 - infona.pl
For the next technological generations of integrated circuits, the traditional challenges faced
by etch plasmas (profile control, selectivity, critical dimensions, uniformity, defects,…) …

Patterning of narrow porous SiOCH trenches using a TiN hard mask

M Darnon, T Chevolleau, D Eon… - Microelectronic …, 2008 - hal.univ-grenoble-alpes.fr
For the next technological generations of integrated circuits, the traditional challenges faced
by etch plasmas (profile control, selectivity, critical dimensions, uniformity, defects,…) …

[PDF][PDF] Patterning of narrow porous SiOCH trenches using a TiN hard mask

M Darnon, T Chevolleau, D Eon, R Bouyssou… - hal.science
For the next technological generations of integrated circuits, the traditional challenges faced
by etch plasmas (profile control, selectivity, critical dimensions, uniformity, defects,...) …

[引用][C] Patterning of narrow porous SiOCH trenches using a TiN hard mask

M DARNON, T CHEVOLLEAU, D EON… - Microelectronic …, 2008 - Elsevier