Patterning of silicon nitride for CMOS gate spacer technology. III. Investigation of synchronously pulsed CH3F/O2/He plasmas

R Blanc, F Leverd, M Darnon, G Cunge… - Journal of Vacuum …, 2014 - pubs.aip.org
Si 3 N 4 spacer etching processes are one of the most critical steps of transistor fabrication
technologies since they must be at the same time very anisotropic to generate straight …
被引用次数：18 相关文章

[引用][C] Patterning of silicon nitride for CMOS gate spacer technology. III. Investigation of synchronously pulsed CH3F/O2/He plasmas

R Blanc, F Leverd, M Darnon… - Journal of Vacuum …, 2014 - hal.univ-grenoble-alpes.fr
Patterning of silicon nitride for CMOS gate spacer technology. III. Investigation of synchronously
pulsed CH3F/O2/He plasmas - Université Grenoble Alpes Accéder directement au contenu …
[PDF] researchgate.net

[PDF][PDF] Patterning of silicon nitride for CMOS gate spacer technology. III. Investigation of synchronously pulsed CH 3 F/O 2/He plasmas

R Blanc, F Leverd, M Darnon, G Cunge… - Journal of Vacuum …, 2014 - researchgate.net
Si3N4 spacer etching processes are one of the most critical steps of transistor fabrication
technologies since they must be at the same time very anisotropic to generate straight …

[引用][C] Patterning of silicon nitride for CMOS gate spacer technology. III. Investigation of synchronously pulsed CH3F/O2/He plasmas

R Blanc, F Leverd, M Darnon, G Cunge… - Journal of Vacuum …, 2014 - cir.nii.ac.jp
Patterning of silicon nitride for CMOS gate spacer technology. III. Investigation of
synchronously pulsed CH3F/O2/He plasmas | CiNii Research CiNii 国立情報学研究所 学術 …

[引用][C] Patterning of silicon nitride for CMOS gate spacer technology. III. Investigation of synchronously pulsed CH3F/O2/He plasmas

R Blanc, F Leverd, M Darnon, G Cunge… - Journal of Vacuum …, 2014 - hal.science
Patterning of silicon nitride for CMOS gate spacer technology. III. Investigation of synchronously
pulsed CH3F/O2/He plasmas - Archive ouverte HAL Accéder directement au contenu …

Patterning of silicon nitride for CMOS gate spacer technology. III. Investigation of synchronously pulsed CH3F/O2/He plasmas

R Blanc, F Leverd, M Darnon, G Cunge… - Journal of Vacuum …, 2014 - pubs.aip.org
Si3N4 spacer etching processes are one of the most critical steps of transistor fabrication
technologies since they must be at the same time very anisotropic to generate straight …

[引用][C] Patterning of silicon nitride for CMOS gate spacer technology. III. Investigation of synchronously pulsed CH3F/O2/He plasmas

R Blanc, F Leverd, M Darnon… - Journal of Vacuum …, 2014 - ui.adsabs.harvard.edu
Patterning of silicon nitride for CMOS gate spacer technology. III. Investigation of synchronously
pulsed CH3F/O2/He plasmas - NASA/ADS Now on home page ads icon ads Enable full ADS …

[引用][C] Patterning of silicon nitride for CMOS gate spacer technology. III. Investigation of synchronously pulsed CH3F/O2/He plasmas

R Blanc, F Leverd, M Darnon… - Journal of Vacuum …, 2014 - hal.univ-grenoble-alpes.fr
Patterning of silicon nitride for CMOS gate spacer technology. III. Investigation of synchronously
pulsed CH3F/O2/He plasmas - Université Grenoble Alpes Accéder directement au contenu …