Energy consumed for transferring data across the processor memory hierarchy constitutes a
large fraction of total system energy consumption, and this fraction has steadily increased …

The performance of computer systems is often limited by the bandwidth of their memory
channels, but further increasing the bandwidth is challenging under the stringent pin and …

This paper introduces a new DRAM design that enables fast and energy-efficient bulk data
movement across subarrays in a DRAM chip. While bulk data movement is a key operation …

The capacity and cost-per-bit of DRAM have historically scaled to satisfy the needs of
increasingly large and complex computer systems. However, DRAM latency has remained …

This paper describes a comprehensive approach for using the memory controller to improve
DRAM energy efficiency and manage DRAM power. We make three contributions:(1) we …

The widespread use of multicore processors has dramatically increased the demand on
high memory bandwidth and large memory capacity. As DRAM subsystem designs stretch to …

DRAM vendors have traditionally optimized the cost-per-bit metric, often making design
decisions that incur energy penalties. A prime example is the overfetch feature in DRAM …

Specialized hardware acceleration is an effective technique to mitigate the dark silicon
problems. A challenge in designing on-chip hardware accelerators for data-intensive …

This paper introduces a 3D-stacked logic-in-memory (LiM) system that integrates the 3D die-
stacked DRAM architecture with the application-specific LiM IC to accelerate important data …

Dynamic Random Access Memory (DRAM) is used as the bulk of the main memory in most
computing systems and its energy and power consumption has become a first-class design …