In an embodiment, a processor may implement an access map-pattern match (AMPM)-
based prefetch circuit for a multi-level cache system. The access patterns that are matched …

In an embodiment, a processor may implement an access map-pattern match (AMPM)-
based prefetch circuit for a multi-level cache system. The access patterns that are matched …

A processor employs a first instruction cache, a second instruction cache, and a fetch unit
employing a fetch/prefetch method among the first and second instruction caches designed …

In an embodiment, a processor may implement an access map-pattern match (AMPM)-
based prefetcher with features designed to improve prefetching accuracy and/or reduce …

Various embodiments of a prefetch unit for use with a cache Subsystem are disclosed. In
one embodiment, the prefetch unit includes a stream storage coupled to a prefetch unit. The …

In an embodiment, a processor includes a plurality of prefetch circuits configured to prefetch
data into a data cache. A primary prefetch circuit may be configured to generate first prefetch …

In an embodiment, a prefetch circuit may implement prefetch “boosting” to reduce the cost of
cold (compulsory) misses and thus potentially improve performance. When a demand miss …

According to one general aspect, an apparatus may include a multi-tiered cache system that
includes at least one upper cache tier relatively closer, hierarchically, to a processor and at …

In an embodiment, a processor may implement an access map-pattern match (AMPM)-
based prefetch circuit with features designed to improve prefetching accuracy and/or reduce …

In an embodiment, a processor may implement an access map-pattern match (AMPM)-
based prefetch circuit with features designed to improve prefetching accuracy and/or reduce …