The aim of this article is to describe a complete partitioning and floorplanning algorithm
tailored for reconfigurable architectures deployable on FPGAs and considering …

The floor planning activity is a key step in the design of systems on FPGAs, but the
approaches available today rarely consider both the constraints imposed by the …

Floorplanning is a mandatory step in the design of hardware accelerators for FPGA
platforms, especially when adopting dynamic partial reconfiguration (DPR). This paper …

When dealing with partially reconfigurable designs on field-programmable gate array,
floorplanning represents a critical step that highly impacts system's performance and …

This work presents a novel floor planner tailored for Partially-Reconfigurable FPGAs having
an arbitrary distribution of heterogeneous resources. The proposed approach precomputes …

The aim of this paper is to show a novel floorplanner based on Mixed-Integer Linear
Programming (MILP), providing a suitable formulation that makes the problem tractable …

The proposed work aims at identifying groups of Reconfigurable Functional Units that are
likely to be configured in the same chip area, identifying these areas based on resource …

Partial reconfiguration on heterogeneous field-programmable gate arrays with millions of
gates yields better utilization of its different types of resources by swapping in and out the …

When floorplanning a reconfigurable system on an FPGA, we have to identify the area of the
device in which modules share resources over time. This process should minimize internal …

Partial dynamic reconfiguration is an emerging area in field programmable gate arrays
(FPGA) designs, which is used for saving device area and cost. In order to reduce the …