A network-on-chip and a corresponding method are provided. The network-on-chip includes
at least one bufferless ring network in at least one dimension of the network-on-chip. At least …

A network-on-chip apparatus including a plurality of network interfaces being independently
connected to a plurality of processing elements; a network including a plurality of switches …

Provided is an on-chip network device which basically operates in a packet switching
network mode, establishes an exclusive communication path according to a request for a …

Primary Examiner—Alpus H Hsu (74) Attorney, Agent, or Firm—Patent Capital Group (57)
ABSTRACT A router of a network-on-chip receives delay information associated with a …

A GALS-based network-on-chip (NoC) includes a plurality of asynchronous first-in first-out
(FIFO) input buffers connected to a plurality of IPs that asynchronously receive data; a …

A switching device of NoC (Networks on Chip) system and a scheduling method thereof. The
switching device has a switching part having a plurality of input ports and a plurality of output …

There are provided a method of creating an optimized core tile-switch mapping architecture
in an on-chip bus and a computer-readable recording medium for recording the method. The …

The main purpose of the present invention is to provide multiple data transfer paths in
parallel with a dynamic con figuration between multiple processor cores or multiple func …

(57) ABSTRACT A method for optimizing a binary tree includes: sequentially searching a
binary tree having IP modules of an on-chip network as the lowermost child nodes in a …

(57) ABSTRACT A method for dynamical adjusting channel direction and Net work-on-Chip
architecture thereof are provided. The Net work-on-Chip architecture of dynamical adjusting …