Drisa: A dram-based reconfigurable in-situ accelerator

S Li, D Niu, KT Malladi, H Zheng, B Brennan… - Proceedings of the 50th …, 2017 - dl.acm.org
Data movement between the processing units and the memory in traditional von Neumann
architecture is creating the" memory wall" problem. To bridge the gap, two approaches, the …

Redram: A reconfigurable processing-in-dram platform for accelerating bulk bit-wise operations

S Angizi, D Fan - 2019 IEEE/ACM International Conference on …, 2019 - ieeexplore.ieee.org
In this paper, we propose ReDRAM, as a reconfigurable DRAM-based processing-in-
memory (PIM) accelerator, which transforms current DRAM architecture to massively parallel …

Eyeriss: An energy-efficient reconfigurable accelerator for deep convolutional neural networks

YH Chen, T Krishna, JS Emer… - IEEE journal of solid-state …, 2016 - ieeexplore.ieee.org
Eyeriss is an accelerator for state-of-the-art deep convolutional neural networks (CNNs). It
optimizes for the energy efficiency of the entire system, including the accelerator chip and off …

iPIM: Programmable in-memory image processing accelerator using near-bank architecture

P Gu, X Xie, Y Ding, G Chen, W Zhang… - 2020 ACM/IEEE 47th …, 2020 - ieeexplore.ieee.org
Image processing is becoming an increasingly important domain for many applications on
workstations and the datacenter that require accelerators for high performance and energy …

Scope: A stochastic computing engine for dram-based in-situ accelerator

S Li, AO Glova, X Hu, P Gu, D Niu… - 2018 51st Annual …, 2018 - ieeexplore.ieee.org
Memory-centric architecture, which bridges the gap between compute and memory, is
considered as a promising solution to tackle the memory wall and the power wall. Such …

DrAcc: A DRAM based accelerator for accurate CNN inference

Q Deng, L Jiang, Y Zhang, M Zhang… - Proceedings of the 55th …, 2018 - dl.acm.org
Modern Convolutional Neural Networks (CNNs) are computation and memory intensive.
Thus it is crucial to develop hardware accelerators to achieve high performance as well as …

McDRAM v2: In-dynamic random access memory systolic array accelerator to address the large model problem in deep neural networks on the edge

S Cho, H Choi, E Park, H Shin, S Yoo - IEEE Access, 2020 - ieeexplore.ieee.org
The energy efficiency of accelerating hundreds of MB-large deep neural networks (DNNs) in
a mobile environment is less than that of a server-class big chip accelerator because of the …

[PDF][PDF] pluto: In-dram lookup tables to enable massively parallel general-purpose computation

JD Ferreira, G Falcao, J Gómez-Luna… - arXiv preprint arXiv …, 2021 - academia.edu
Data movement between main memory and the processor is a significant contributor to the
execution time and energy consumption of memory-intensive applications. This data …

Chameleon: Versatile and practical near-DRAM acceleration architecture for large memory systems

H Asghari-Moghaddam, YH Son… - 2016 49th annual …, 2016 - ieeexplore.ieee.org
The performance of computer systems is often limited by the bandwidth of their memory
channels, but further increasing the bandwidth is challenging under the stringent pin and …

RANA: Towards efficient neural acceleration with refresh-optimized embedded DRAM

F Tu, W Wu, S Yin, L Liu, S Wei - 2018 ACM/IEEE 45th Annual …, 2018 - ieeexplore.ieee.org
The growing size of convolutional neural networks (CNNs) requires large amounts of on-
chip storage. In many CNN accelerators, their limited on-chip memory capacity causes …