Direct access,{High-Performance} memory disaggregation with {DirectCXL}
New cache coherent interconnects such as CXL have recently attracted great attention
thanks to their excellent hardware heterogeneity management and resource disaggregation …
thanks to their excellent hardware heterogeneity management and resource disaggregation …
Hoti 2019: Compute express link
S Van Doren - 2019 IEEE Symposium on High-Performance …, 2019 - ieeexplore.ieee.org
Summary form only given. Compute Express Link (CXL) is an open industry standard
interconnect offering high-bandwidth, low latency connectivity between host processors and …
interconnect offering high-bandwidth, low latency connectivity between host processors and …
Thymesisflow: A software-defined, hw/sw co-designed interconnect stack for rack-scale memory disaggregation
C Pinto, D Syrivelis, M Gazzetti… - 2020 53rd Annual …, 2020 - ieeexplore.ieee.org
With cloud providers constantly seeking the best infrastructure trade-off between
performance delivered to customers and overall energy/utilization efficiency of their data …
performance delivered to customers and overall energy/utilization efficiency of their data …
Why on-chip cache coherence is here to stay
Why on-chip cache coherence is here to stay Page 1 78 CommuniCations oF the aCm | juLy 2012
| voL. 55 | no. 7 contributed articles shAred MeMorY is the dominant low-level communication …
| voL. 55 | no. 7 contributed articles shAred MeMorY is the dominant low-level communication …
SCD: A scalable coherence directory with flexible sharer set encoding
D Sanchez, C Kozyrakis - IEEE International Symposium on …, 2012 - ieeexplore.ieee.org
Large-scale CMPs with hundreds of cores require a directory-based protocol to maintain
cache coherence. However, previously proposed coherence directories are hard to scale …
cache coherence. However, previously proposed coherence directories are hard to scale …
Hello bytes, bye blocks: PCIe storage meets compute express link for memory expansion (CXL-SSD)
M Jung - Proceedings of the 14th ACM Workshop on Hot Topics …, 2022 - dl.acm.org
Compute express link (CXL) is the first open multi-protocol method to support cache
coherent interconnect for different processors, accelerators, and memory device types. Even …
coherent interconnect for different processors, accelerators, and memory device types. Even …
Jigsaw: Scalable software-defined caches
N Beckmann, D Sanchez - Proceedings of the 22nd …, 2013 - ieeexplore.ieee.org
Shared last-level caches, widely used in chip-multi-processors (CMPs), face two
fundamental limitations. First, the latency and energy of shared caches degrade as the …
fundamental limitations. First, the latency and energy of shared caches degrade as the …
SWAP: Effective fine-grain management of shared last-level caches with minimum hardware support
Performance isolation is an important goal in server-class environments. Partitioning the last-
level cache of a chip multiprocessor (CMP) across co-running applications has proven …
level cache of a chip multiprocessor (CMP) across co-running applications has proven …
KPart: A hybrid cache partitioning-sharing technique for commodity multicores
Cache partitioning is now available in commercial hardware. In theory, software can
leverage cache partitioning to use the last-level cache better and improve performance. In …
leverage cache partitioning to use the last-level cache better and improve performance. In …
Cooperative cache partitioning for chip multiprocessors
J Chang, GS Sohi - ACM International Conference on Supercomputing …, 2007 - dl.acm.org
This paper presents Cooperative Cache Partitioning (CCP) to allocate cache resources
among threads concurrently running on CMPs. Unlike cache partitioning schemes that use a …
among threads concurrently running on CMPs. Unlike cache partitioning schemes that use a …