A physics-based single event transient pulse width model for CMOS VLSI circuits

YM Aneesh, B Bindu - IEEE Transactions on Device and …, 2020 - ieeexplore.ieee.org
The single-event transients in MOSFETs due to heavy ion strikes introduce soft errors in sub-
50 nm CMOS VLSI circuits. These transients are easily captured and propagated in high …

An analytical model of single-event transients in double-gate MOSFET for circuit simulation

YM Aneesh, SR Sriram, KR Pasupathy… - IEEE Transactions on …, 2019 - ieeexplore.ieee.org
In this paper, a physics-based bias-dependent model of single-event transients (SETs) in
double-gate (DG) MOSFET suitable for circuit simulation is presented. The existing …

Physically based predictive model for single event transients in CMOS gates

M Saremi, A Privat, HJ Barnaby… - IEEE Transactions on …, 2016 - ieeexplore.ieee.org
An analytical model is presented to understand the time response of an inverter to ionizing
particles based on physical equations. The model divides the output voltage transient …

Characterization of the effect of pulse quenching on single-event transients in 65-nm twin-well and triple-well CMOS technologies

J Chen, J Yu, P Yu, B Liang… - IEEE Transactions on …, 2018 - ieeexplore.ieee.org
As chip technologies scale down in size, multiple adjacent logic nodes are often affected by
a single high-energy ion strike. The so-called pulse quenching effect, induced by single …

Effect of multiple-transistor charge collection on single-event transient pulse widths

JR Ahlbin, MJ Gadlage, NM Atkinson… - … on Device and …, 2011 - ieeexplore.ieee.org
Heavy-ion data from a 130-nm bulk CMOS process shows a counterproductive result in
using a common single-event charge collection mitigation technique. Guard bands, which …

Modeling and analysis of single-event transient sensitivity of a 65 nm clock tree

Y Li, L Chen, I Nofal, M Chen, H Wang, R Liu… - Microelectronics …, 2018 - Elsevier
The soft error rate (SER) due to heavy-ion irradiation of a clock tree is investigated in this
paper. A method for clock tree SER prediction is developed, which employs a dedicated soft …

Characterization and modelling of single event transients in LDMOS-SOI FETs

J Alvarado, V Kilchytska, E Boufouss… - Microelectronics …, 2011 - Elsevier
In this paper, we develop a model to simulate the single event transient (SET) phenomena in
LDMOS-SOI devices. 3D simulations and compact model are coupled in order to reproduce …

Voltage dependency of propagating single-event transient pulsewidths in 90-nm CMOS technology

J Qin, S Chen, B Liang, Z Ge, Y He, Y Du… - … on Device and …, 2013 - ieeexplore.ieee.org
This paper reports on the supply voltage dependency of single-event transient (SET)
propagation and multinode charge collection phenomena in integrated circuits. We have …

Single-event transient measurements in nMOS and pMOS transistors in a 65-nm bulk CMOS technology at elevated temperatures

MJ Gadlage, JR Ahlbin, B Narasimham… - … on Device and …, 2010 - ieeexplore.ieee.org
In this paper, heavy-ion-induced single-event transient (SET) pulsewidths measured in a 65-
nm bulk CMOS technology at temperatures ranging from 25° C to 100° C with an …

Characterization of single-event transients induced by high LET heavy ions in 16 nm bulk FinFET inverter chains

Y Chi, Z Wu, P Huang, Q Sun, B Liang, Z Zhao - Microelectronics Reliability, 2022 - Elsevier
Single-event transient (SET) distributions and cross-sections are characterized for 16 nm
bulk FinFET inverters with different threshold voltages and driving strengths using the heavy …