Over the past decade, the primary focus for improving the performance of nano-electronic
metal interconnect structures has been to reduce the impact of resistance-capacitance (RC) …

In accordance with a preferred embodiment of the invention, there is disclosed a method for
fabricating an integrated circuit including a plurality of metal layerS Sepa rated by dielectric …

Current status and challenges of aggressive equivalent-oxide-thickness (EOT) scaling of
high-κ gate dielectrics via higher-κ (> 20) materials and interfacial layer (IL) scavenging …

High-κ Dielectric Materials for Microelectronics Page 1 Critical Reviews in Solid State and
Materials Sciences, 28:231–285, 2003 Copyright C Taylor and Francis Inc. ISSN: 1040-8436 …

High-κ gate dielectrics like HfO2 and HfSiO (N) are considered for the replacement of SiO2
and SiON layers in advanced complementary metal–oxide–semiconductor (MOS) devices …

Continued reduction in resistance-capacitance (RC) delays in nano-electronic Cu
interconnect structures will require new materials with increasingly lower dielectric constants …

Continuing improvement in device density and performance has significantly affected the
dimensions and complexity of the wiring structure for on-chip interconnects. These …

2. Description of Related Art Because of continuing decreases in size of circuit com ponents
in semiconductor chips, there are a number of interconnect wiring challenges facing the …

Integrated circuits (ICs) are fabricated on wafers of a semiconductor material Such as silicon.
As many integrated circuit devices as possible are placed on the wafer to maximize the …

The drive toward smaller and smaller electronic componentry has huge implications for the
materials currently being used. As quantum mechanical effects begin to dominate …