An area efficient and robust integrated test core for mixed-signal circuits is described. The
core consists of a completely digital implementation, except for a simple reconstruction filter …

This paper presents significant improvements in the generation of analog signals for on-chip
analog circuit testing. In particular the novel oscillators proposed here can achieve signal-to …

The simultaneous operation of multiple embedded analog test cores is investigated through
experiments on a prototype integrated circuit containing eight such cores. Each core …

This paper presents the design of an on-chip spectrum analyzer. A novel architecture is
used to mitigate the problems encountered in trying to implement architectures employed in …

A novel digital functional test system architecture, called Sequencer Per Pin in which the
timing and waveform generation hardware work with a sequence of events in the same …

This paper describes a test application for an IC with over 200 logic signals each carrying
multiple-gigahertz data. An aggregate data rate approaching a terabit-per-second is attained …

High-speed digital design is becoming increasingly analog. In particular, interconnect
response at high frequencies can be non-monotonic with" porch steps" and ringing …

We propose a comprehensive built-in self-test (BIST) methodology for analog and mixed-
signal circuits. A time-division multiplexing (TDM) comparator scheme was proposed as an …

This paper describes basic requirements for a standard bus for testing analog interconnects.
The viewpoint is that of prospective users. An architecture for such a standard bus is …

A multi-purpose digital test core utilizing programmable logic has been introduced [1, 2] to
implement many of the functions of traditional automated test equipment (ATE). While …