A P-channel single-poly non-volatile memory cell having P+ source and P+ drain regions
and a channel extending therebetween is formed in an N-type well. An overlying poly-silicon …

A single-poly, floating gate memory cell includes a PMOS write and an NMOS read path.
The memory cell's write path includes a PMOS half-transistor coupled in series with a PMOS …

SUMMARY A single-poly memory cell is disclosed herein which overcomes problems in the
art described above. In accor dance with the present invention, a P-channel single-poly flash …

SUMMARY A Single-poly memory cell is disclosed herein which overcomes problems in the
art described above. In accor dance with the present invention, a P-channel Single-poly …

A single-poly PMOS nonvolatile memory (NVM) cell and a method of programming, erasing
and reading such a cell are implemented using a single-poly PMOS NVM cell which …

A single-poly non-volatile memory includes a PMOS select transistor (210) formed with a
select gate (212), and P+ source and drain regions (211, 213) formed in a shared n-well …

Abstract A P-channel MOS memory cell has P+ source and drain regions formed in an N-
well. A thin runnel oxide is provided between the well surface and an overlying floating gate …

A high density single-poly metal-gate non-volatile memory cell uses a layer of tunnel oxide
formed over a silicon substrate. A floating gate is formed over the tunnel oxide. Source and …

A nonvolatile memory integrated circuit arrayed in rows and columns is disclosed. Parallel
lines of implant N-type regions are formed in a P-well of a semiconductor substrate, with …

Implementing modified souce/drain implants in a non-volatile memory process while leaving
the source/drain regions in the memory cells of the device unmodified and adding no critical …