SpecuSym: Speculative symbolic execution for cache timing leak detection

S Guo, Y Chen, P Li, Y Cheng, H Wang, M Wu… - Proceedings of the ACM …, 2020 - dl.acm.org
CPU cache is a limited but crucial storage component in modern processors, whereas the
cache timing side-channel may inadvertently leak information through the physically …

Adversarial symbolic execution for detecting concurrency-related cache timing leaks

S Guo, M Wu, C Wang - Proceedings of the 2018 26th ACM Joint …, 2018 - dl.acm.org
The timing characteristics of cache, a high-speed storage between the fast CPU and the
slow memory, may reveal sensitive information of a program, thus allowing an adversary to …

CANAL: a cache timing analysis framework via LLVM transformation

C Sung, B Paulsen, C Wang - Proceedings of the 33rd ACM/IEEE …, 2018 - dl.acm.org
A unified modeling framework for non-functional properties of a program is essential for
research in software analysis and verification, since it reduces burdens on individual …

Symbolic verification of cache side-channel freedom

S Chattopadhyay… - IEEE Transactions on …, 2018 - ieeexplore.ieee.org
Cache timing attacks allow third-party observers to retrieve sensitive information from
program executions. But, is it possible to automatically check the vulnerability of a program …

Identifying and predicting timing-critical instructions to boost timing speculation

J Xin, R Joseph - Proceedings of the 44th Annual IEEE/ACM …, 2011 - dl.acm.org
Circuit-level timing speculation has been proposed as a technique to reduce dependence
on design margins and eliminating power/performance overheads. Recent work has …

Predicting timing violations through instruction-level path sensitization analysis

S Roy, K Chakraborty - Proceedings of the 49th Annual Design …, 2012 - dl.acm.org
In this paper, we present a novel technique for early prediction of timing violations in high-
performance pipelined microprocessors. We show that a static instruction in a …

Abstract interpretation under speculative execution

M Wu, C Wang - Proceedings of the 40th ACM SIGPLAN Conference on …, 2019 - dl.acm.org
Analyzing the behavior of a program running on a processor that supports speculative
execution is crucial for applications such as execution time estimation and side channel …

Precise cache timing analysis via symbolic execution

DH Chu, J Jaffar, R Maghareh - 2016 IEEE Real-Time and …, 2016 - ieeexplore.ieee.org
We present a framework for WCET analysis of programs with emphasis on cache micro-
architecture. Such an analysis is challenging primarily because of the timing model of a …

DAWG: A defense against cache timing attacks in speculative execution processors

V Kiriansky, I Lebedev, S Amarasinghe… - 2018 51st Annual …, 2018 - ieeexplore.ieee.org
Software side channel attacks have become a serious concern with the recent rash of
attacks on speculative processor architectures. Most attacks that have been demonstrated …

Data cache locking for tight timing calculations

X Vera, B Lisper, J Xue - ACM Transactions on Embedded Computing …, 2007 - dl.acm.org
Caches have become increasingly important with the widening gap between main memory
and processor speeds. Small and fast cache memories are designed to bridge this …