Understanding reduced-voltage operation in modern DRAM devices: Experimental characterization, analysis, and mechanisms
The energy consumption of DRAM is a critical concern in modern computing systems.
Improvements in manufacturing process technology have allowed DRAM vendors to lower …
Improvements in manufacturing process technology have allowed DRAM vendors to lower …
What your DRAM power models are not telling you: Lessons from a detailed experimental study
Main memory (DRAM) consumes as much as half of the total system power in a computer
today, due to the increasing demand for memory capacity and bandwidth. There is a …
today, due to the increasing demand for memory capacity and bandwidth. There is a …
Refresh now and then
DRAM stores information in electric charge. Because DRAM cells lose stored charge over
time due to leakage, they have to be “refreshed” in a periodic manner to retain the stored …
time due to leakage, they have to be “refreshed” in a periodic manner to retain the stored …
DRAM bender: An extensible and versatile FPGA-based infrastructure to easily test state-of-the-art DRAM chips
To understand and improve DRAM performance, reliability, security, and energy efficiency,
prior works study characteristics of commodity DRAM chips. Unfortunately, state-of-the-art …
prior works study characteristics of commodity DRAM chips. Unfortunately, state-of-the-art …
Design-induced latency variation in modern DRAM chips: Characterization, analysis, and latency reduction mechanisms
Variation has been shown to exist across the cells within a modern DRAM chip. Prior work
has studied and exploited several forms of variation, such as manufacturing-process-or …
has studied and exploited several forms of variation, such as manufacturing-process-or …
Understanding latency variation in modern DRAM chips: Experimental characterization, analysis, and optimization
Long DRAM latency is a critical performance bottleneck in current systems. DRAM access
latency is defined by three fundamental operations that take place within the DRAM cell …
latency is defined by three fundamental operations that take place within the DRAM cell …
A validation of DRAM RAPL power measurements
S Desrochers, C Paradis, VM Weaver - Proceedings of the Second …, 2016 - dl.acm.org
Recent Intel processors support the Running Average Power Level (RAPL) interface, which
among other things provides estimated energy measurements for the CPUs, integrated …
among other things provides estimated energy measurements for the CPUs, integrated …
Solar-DRAM: Reducing DRAM access latency by exploiting the variation in local bitlines
DRAM latency is a major bottleneck for many applications in modern computing systems. In
this work, we rigorously characterize the effects of reducing DRAM access latency on 282 …
this work, we rigorously characterize the effects of reducing DRAM access latency on 282 …
Flikker: Saving DRAM refresh-power through critical data partitioning
S Liu, K Pattabiraman, T Moscibroda… - Proceedings of the …, 2011 - dl.acm.org
Energy has become a first-class design constraint in computer systems. Memory is a
significant contributor to total system power. This paper introduces Flikker, an application …
significant contributor to total system power. This paper introduces Flikker, an application …
Adaptive-latency DRAM: Optimizing DRAM timing for the common-case
In current systems, memory accesses to a DRAM chip must obey a set of minimum latency
restrictions specified in the DRAM standard. Such timing parameters exist to guarantee …
restrictions specified in the DRAM standard. Such timing parameters exist to guarantee …