Memory Hierarchy Optimization in Embedded Systems using On-Chip SRAM
JW Kim, SK Kim, JJ Lee, CH Jung… - Journal of KIISE …, 2009 - koreascience.kr
The memory wall is the growing disparity of speed between CPU and memory outside the
CPU chip. An economical solution is a memory hierarchy organized into several levels, such …
CPU chip. An economical solution is a memory hierarchy organized into several levels, such …
A novel design of software system on chip for embedded system
More and more transistors are integrated onto a single chip. Embedded systems have
powerful cores compared with traditional ones. On-chip SRAM is also integrated to provide …
powerful cores compared with traditional ones. On-chip SRAM is also integrated to provide …
[引用][C] On-Chip Memory Optimization for Linux Kernel
J Wu, P Fang, M Ling, Y Zhang - Weidianzixue …, 2012 - Sichuan Institute of Solid State …
Alternative choice for energy optimization in embedded system
W Liqin, S Lin - 2009 IEEE/INFORMS International Conference …, 2009 - ieeexplore.ieee.org
Effective utilization of on chip storage space is important for reduction of memory subsystem
energy consumptions of embedded systems which are powered by batteries. In the past …
energy consumptions of embedded systems which are powered by batteries. In the past …
Reducing memory system energy by software-controlled on-chip memory
M Kondo, H Nakamura - IEICE transactions on electronics, 2003 - search.ieice.org
In recent computer systems, a large portion of energy is consumed by on-chip cache
accesses and data movement between cache and off-chip main memory. Reducing these …
accesses and data movement between cache and off-chip main memory. Reducing these …
Reducing Energy Consumption by Code Repositioning for Memory Levels
A Balasundaram, V Chenniappan - Asian Journal of Research …, 2017 - indianjournals.com
The valuable time of the core processor is lost for fetching the data to/from memory, when
attached to relatively slow memory devices and this issue is termed as Memory Wall …
attached to relatively slow memory devices and this issue is termed as Memory Wall …
Fast and accurate code placement of embedded software for hybrid on-chip memory architecture
On chip SRAMs including scratchpad memories (SPMs) and caches are widely used in
embedded systems to narrow the speed gap between CPU and memory. Memory …
embedded systems to narrow the speed gap between CPU and memory. Memory …
An ILP Model of Code Placement Problem for Minimizing the Energy Consumption in Embedded Processors
Y Ishitobi, T Ishihara, H Yasuura - IEICE Technical Report; IEICE Tech …, 2007 - ken.ieice.org
(in English) This paper formulates a code placement problem to optimize the total energy
consumption of a CPU core, on-chip memories and off-chip memories in embedded …
consumption of a CPU core, on-chip memories and off-chip memories in embedded …
[引用][C] Low Power Strategy Based on Threshold Prediction for Linux Sleep Mode
W Shang, J Wu, L Zhang - Weidianzixue …, 2013 - Sichuan Institute of Solid State …