An apparatus includes a cache controller circuit and a multi-ported cache memory including
a plurality of cache ways. The cache controller circuit is configured to maintain rank values …

An apparatus for using a dataless cache entry includes a cache memory and a cache
controller configured to identify a first cache entry in cache memory as a potential cache …

An apparatus includes a cache memory circuit configured to store a cache lines, and a
cache controller circuit. The cache controller circuit is configured to receive a read request to …

A cache memory and method of operating a cache memory are provided. The cache
memory comprises cache storage that stores cache lines for a plurality of requesters and …

A cache is provided having a plurality of entries for storing data. In response to a given
access request, lookup circuitry performs a lookup operation in the cache to determine …

Disclosed herein is a method for operating access to a cache memory via an effective
address comprising a tag field and a cache line index field. The method comprises: splitting …

Disclosed herein is a method for operating access to a cache memory via an effective
address comprising a tag field and a cache line index field. The method comprises: splitting …

Disclosed herein is a method for operating access to a cache memory via an effective
address comprising a tag field and a cache line index field. The method comprises: splitting …

An apparatus and method are described, the apparatus comprising: a cache comprising a
plurality of entries, each associated with a partition identifier; storage circuitry to store …

A cache memory includes a cache array including a plurality of congruence classes each
containing a plurality of cache lines, where each cache line belongs to one of multiple …