Machine Learning-Based Soft-Error-Rate Evaluation for Large-Scale Integrated Circuits

R Song, J Shao, Y Chi, B Liang, J Chen, Z Wu - Electronics, 2023 - mdpi.com
Transient pulses generated by high-energy particles can cause soft errors in circuits,
resulting in spacecraft malfunctions and posing serious threats to the normal operation of …

DMBF: Design metrics balancing framework for soft-error-tolerant digital circuits through bayesian optimization

Y Li, C Chen, X Cheng, J Han… - IEEE Transactions on …, 2023 - ieeexplore.ieee.org
Radiation Hardened by Design (RHBD) is one of the main measures for solving the soft
error issue in digital circuits. However, a multi-objective optimization (MOO) problem …

Soft error rate estimation of combinational circuits based on vulnerability analysis

M Raji, H Pedram, B Ghavami - IET Computers & Digital …, 2015 - Wiley Online Library
Nanometer integrated circuits are getting increasingly vulnerable to soft errors and making
the soft error rate (SER) estimation an important challenge. In this study, a novel approach is …

Layout-aware soft error rate estimation technique for integrated circuits under the environment with energetic charged particles

AO Balbekov, MS Gorbunov… - Journal of Physics …, 2017 - iopscience.iop.org
Abstract Single Event Transient (SET) is a current and voltage disturbance in an integrated
circuit (IC), caused by charged particle impact. In modern IC technologies single charged …

Accelerating soft-error-rate (ser) estimation in the presence of single event transients

J Li, J Draper - Proceedings of the 53rd Annual Design Automation …, 2016 - dl.acm.org
Radiation-induced soft errors have posed an ever increasing reliability challenge as device
dimensions keep shrinking in advanced CMOS technology. Therefore, it is imperative to …

A fast statistical soft error rate estimation method for nano-scale combinational circuits

M Raji, B Ghavami - Journal of Electronic Testing, 2016 - Springer
Nano-scale digital integrated circuits are getting increasingly vulnerable to soft errors due to
aggressive technology scaling. On the other hand, the impacts of process variations on …

Soft error rate reduction of combinational circuits using gate sizing in the presence of process variations

M Raji, B Ghavami - IEEE Transactions on Very Large Scale …, 2016 - ieeexplore.ieee.org
Soft errors in combinational logic circuits are emerging as a significant reliability concern for
nanoscale VLSI designs. This paper presents a novel sensitivity-based gate sizing …

Aging-aware soft error rate analysis for nano-scaled CMOS circuits

A Yan, H Liang, Z Huang, C Jiang - Journal of Computer-Aided Design & …, 2015 - jcad.cn
Technology scaling results in that the sensitivity of combinational circuits to soft errors and
negative bias temperature instability (NBTI) effect to circuits is becoming more and more …

Layout-based soft error rate estimation framework considering multiple transient faults—From device to circuit level

HM Huang, CHP Wen - … Aided Design of Integrated Circuits and …, 2015 - ieeexplore.ieee.org
This paper investigated the soft errors caused by particle strikes, such as high-energy
neutrons, extending beyond the deep submicrometer era. Considering the structure of the …

Statistical soft error rate estimation of combinational circuits using Bayesian networks

MA Sabet, B Ghavami - … -The international journal for computation and …, 2016 - emerald.com
Purpose With continuous scaling of digital circuit CMOS technology, the vulnerability of
these circuits are significantly increasing against the soft errors. On the other hand, the …