YB Kim - transactions on electrical and electronic materials, 2010 - koreascience.kr
Complementary metal-oxide-semiconductor (CMOS) technology scaling has been a main key for continuous progress in silicon-based semiconductor industry over the past three …
Although Si MOS devices have dominated the integrated circuit applications over the four decades, it has been anticipated that the development of CMOS would reach its limits after …
VA Sverdlov, TJ Walls… - IEEE Transactions on …, 2003 - ieeexplore.ieee.org
We have carried out extensive numerical modeling of double-gate, nanoscale silicon n- metal oxide semiconductor field effect transistors (MOSFETs) with ultrathin, intrinsic …
H Iwai - Microelectronic Engineering, 2009 - Elsevier
The down-scaling is still the most important and effective way for achieving the high- performance logic CMOS operation with low power, regardless of its concern for the …
This work covers the impact of dual metal gate engineered Junctionless MOSFET with various high-k dielectric in Nanoscale circuits for low power applications. Due to gate …
KJ Kuhn - IEEE transactions on Electron Devices, 2012 - ieeexplore.ieee.org
This review paper explores considerations for ultimate CMOS transistor scaling. Transistor architectures such as extremely thin silicon-on-insulator and FinFET (and related …
Silicon technology continues to progress, but device scaling is rapidly taking the metal oxide semiconductor field-effect transistor (MOSFET) to its limit. When MOS technology was …