AES is a symmetric encryption algorithm widely used in many applications. An AES
implementation in the data plane can help us build in-network security and privacy …

As networking technology advances, the gap between network bandwidth and network
processing power widens. Information security issues add to the need for developing high …

Abstract In October 2000 the National Institute of Standards and Technology chose Rijndael
algorithm as the new Advanced Encryption Standard (AES). AES finds wide deployment in a …

A fully pipelined implementation of the Advanced Encryption Standard encryption algorithm
with 128-bit input and key length (AES-128) was implemented on Xilinx'Virtex-E and Virtex-II …

We propose an efficient hardware implementation of the advanced encryption standard
algorithm, with key expansion capability. Compared to the widely used table lookup …

This paper presents the outer-round only pipelined architecture for a FPGA implementation
of the AES-128 encryption processor. The proposed design uses the Block RAM storing the …

In this brief, we present a high-speed AES IP-core, which runs at 880 MHz on a 0.13-/spl
mu/m CMOS standard cell library, and which achieves over 10-Gbps throughput in all …

Network applications need to be fast and at the same time provide security. In order to
minimize the overhead of the security algorithm on the performance of the application, the …

This paper addresses a pipelined partial rolling (PPR) architecture for the AES encryption.
The key technique is the PPR architecture, which is suitable for FPGA implementation. Using …

In this paper a compact FPGA architecture for the AES algorithm with 128-bitkey targeted for
low-costembedded applications is presented. Encryption, decryption and key schedule are …