[PDF][PDF] Efficient Implementation of 2-Bit Magnitude Comparator Using PTL

S Bhuvaneswari, R Prabakaran… - International Journal of …, 2017 - academia.edu
Nowadays the requirements of low power electronics play a vital role in various fields. In this
paper we introducing the novel comparator is one of the fundamental units in VLSI design …

[PDF][PDF] A Novel Design of Hybrid 2 Bit Magnitude Comparator

MM Das, G Mohan, AK Greeshma - International Research Journal …, 2019 - academia.edu
With the increasing demand of IoT and portable devices which are battery operated, low
power designs are very essential. Comparator is the most fundamental component that …

[PDF][PDF] Low power magnitude comparator circuit design

V Shekhawat, T Sharma, KG Sharma - International Journal of …, 2014 - academia.edu
This paper presents a new low power 2-Bit magnitude comparator using full adder
technique. The proposed magnitude comparator (PTL logic) has been compared with …

[PDF][PDF] A low power 8-bit magnitude comparator with small transistor count using hybrid ptl/cmos logic

G Sharma, U Nirmal, Y Misra - IJCEM International Journal of …, 2011 - researchgate.net
Magnitude comparison is one of the basic functions used for sorting in microprocessor,
digital signal processing, so a high performance, effective magnitude comparator is …

Design and analysis of low power, high speed 4-bit magnitude comparator

P Singh, PK Jain - 2018 International Conference on Recent …, 2018 - ieeexplore.ieee.org
This paper illustrates the design of low power, high speed 4 Bit Magnitude Comparator. The
NOR gate logic used in this paper to design the proposed circuit can help in designing of …

Evaluation and Performance Analysis of Magnitude Comparator for High-Speed VLSI Applications

MR Machupalli, K Challa, MK Bathula… - Intelligent Systems and …, 2022 - Springer
In the architecture of central processing units (CPUs) and microcontrollers, the magnitude or
the digital comparator plays a vital role. The performance of the comparator sinks due to the …

[PDF][PDF] A Novel Dedicated Low Power 64 Bit Digital Comparator Using Cmos Logic

S Panda, A Behera, MR Jena, S Nath - Journal of Embedded …, 2014 - academia.edu
In this paper we have designed a novel dedicated low power 64 bit digital comparator.
Magnitude comparison is one of the basic functions used for sorting in microprocessor …

A novel design of 12-bit digital comparator using multiplexer for high speed application in 32-nm cmos technology

DN Mukherjee, S Panda, B Maji - IETE Journal of Research, 2022 - Taylor & Francis
In the present scenario, power, speed, and area of an electronic device play a significant
role specifically in the field of modern VLSI technology. In this research, small power …

[PDF][PDF] 2-Bit CMOS comparator by hybridizing PTL and pseudo logic

V Choudhary, R Mehra - International Journal of Recent Technology and …, 2013 - Citeseer
In this paper an area and power efficient hybrid comparator is proposed by hybridizing PTL
and Pseudo logic design. This hybrid comparator is proposed to improve area and power in …

Design and Implementation of Low Power 32-bit Comparator

VR Ratna, R Mariserla - 2021 - papers.ssrn.com
Comparator plays a vital role in many IC applications, Microprocessors, computer systems
etc. Hence it is desirable to design a comparator block with low power consumption and …