Dual threshold voltages domino design methodology utilizes low threshold voltages for all
transistors that can switch during the evaluate mode and utilizes high threshold voltages for …

A sleep switch dual threshold voltage domino logic circuit technique for placing idle domino
circuits into a low leakage state is proposed in this paper. The circuit technique reduces the …

A circuit technique is presented for reducing the subthreshold leakage energy consumption
of domino logic circuits. Sleep switch transistors are proposed to place an idle dual …

Among the assorted logic styles used in fostering the integrated circuits, the domino logic
styles offers higher speed and smaller transistor count as compared to the static cmos …

This paper demonstrate a new design technique for the implementation of sub-threshold
voltage range domino logic gates using MOSFETs. The paper shows the implementation of …

Subthreshold leakage current becomes the major component of total power dissipation as
scaling down the feature size. In this paper, two new circuit techniques are proposed for …

A low swing domino logic technique is proposed to decrease power consumption without
sacrificing noise immunity. With the proposed low swing domino logic circuit technique …

Low threshold voltage (V/sub t/) can be applied to domino logic to improve the performance
in dual threshold voltage technology. Then, the keeper transistor should be up-sized to …

A circuit technique is proposed in this paper for simultaneously reducing the subthreshold
and gate oxide leakage power consumption in domino logic circuits. PMOS-only sleep …

In this paper, a low leakage circuit technique is proposed for simultaneously reducing the
subthreshold and gate oxide leakage power in domino logic circuits. NMOS sleep transistors …