High-Throughput CBC Mode Crypto Circuit

KC Chang, YT Teng, WL Chin - Electrical Science & …, 2023 - journals.bilpubgroup.com
The objective of this study is to investigate a high-throughput cipher-block chaining (CBC)
mode crypto circuit, which can be embedded in commercial home gateways or …

An FPGA based cascaded CBC block cipher through RPSPNC and TE

R Chakraborty, JK Mandal - Microsystem Technologies, 2019 - Springer
Security system can be enhanced by cascading approach where two or more cryptographic
algorithms are applied serially or parallel. In this paper the plaintext is first divided into …

Design and analysis of AES-CBC mode for high security applications

M Vaidehi, BJ Rabi - … on Current Trends In Engineering and …, 2014 - ieeexplore.ieee.org
The challenge in securizing communications networks is to obtain flexible means able to
deal with the intensive computation needed by the cryptography algorithms. A …

Design and Implementation of the Block Cipher-SMS4 IP Core

B Wang, JL Lan, YF Guo, YY Zhang - Advanced Materials …, 2010 - Trans Tech Publ
Block ciphers play an essential role in securing the wireless communications. In this paper,
an FPGA implementation of the new block cipher SMS4 is presented. The SMS4 Intellectual …

[PDF][PDF] A Controllable Parallel CBC Block Cipher Mode of Operation.

K Yuan, K Duanmu, J Ge, B Zhou, C Jia - Journal of Information …, 2024 - jips-k.org
To address the requirement for high-speed encryption of large amounts of data, this study
improves the widely adopted cipher block chaining (CBC) mode and proposes a …

Comparative Study of Block Ciphers Implementation for Resource-Constrained Devices

MS Naik, DK Sreekantha, KV Sairam - … and Communications Systems, 2023 - Springer
Lightweight cryptography (LWC) is critical for securing data between devices with limited
resources. In this paper, we consider hardware-based block ciphers (BC). The BCs are …

[引用][C] An Efficient Implementation of ARIA and AES Block Cipher Algorithms Supporting Four Modes of Operation

KB Kim, WL Cho, YC Jang, KW Shin - 대한전자공학회학술대회, 2017 - dbpia.co.kr
This paper presents a design of crypto-processor implementing two block cipher algorithms,
ARIA and AES. The ARIA-AES crypto-processor supports key length of 128 and 256 bits, as …

The design and implementation of ECC high-speed encryption engine based on FPGA

W Liang, JB Xu, WH Huang, L Peng - Advanced Materials …, 2012 - Trans Tech Publ
Network security technology ensures secure data transmission in network. Meanwhile, it
brings extra overhead of security system in terms of cost and performance, which seriously …

High-speed block cipher algorithm based on hybrid method

B Do Thi, MN Hieu - Ubiquitous Information Technologies and Applications …, 2014 - Springer
This paper proposes 3 different designs of the new 64-bit block cipher diagram. A new
feature of the designs is the application of hybrid CSPN (Controlled Substitution Permutation …

Design and Implementation of Unified Hardware for 128‐Bit Block Ciphers ARIA and AES

B Koo, G Ryu, T Chang, S Lee - ETRI journal, 2007 - Wiley Online Library
ARIA and the Advanced Encryption Standard (AES) are next generation standard block
cipher algorithms of Korea and the US, respectively. This letter presents an area‐efficient …