A V-band power amplifier with 23.7-dBm output power, 22.1% PAE, and 29.7-dB gain in 65-nm CMOS technology

Y Chang, Y Wang, CN Chen, YC Wu… - IEEE Transactions on …, 2019 - ieeexplore.ieee.org
This article presents a V-band three-stage power amplifier (PA) fabricated in 65-nm CMOS
technology with remarkable performances of output power, efficiency, and power gain. A …

Three‐stage transformer‐coupled CMOS power amplifier for millimeter‐wave applications using 130 nm CMOS technology

M Mansour, I Mansour - International Journal of Circuit Theory …, 2022 - Wiley Online Library
High‐efficiency and high‐linearity three‐stage transformer‐coupled power amplifier (PA)
and power combiner for millimeter‐wave applications using 130 nm CMOS technology are …

A 60-GHz CMOS dual-mode power amplifier with efficiency enhancement at low output power

L Kuang, B Chi, H Jia, W Jia… - IEEE Transactions on …, 2015 - ieeexplore.ieee.org
A 60-GHz dual-mode power amplifier (PA) with efficiency enhancement at low output power
in 65-nm bulk CMOS is presented. The PA consists of two cascaded common-source driver …

A 60-GHz dual-mode class AB power amplifier in 40-nm CMOS

D Zhao, P Reynaert - IEEE Journal of Solid-State Circuits, 2013 - ieeexplore.ieee.org
A 60-GHz dual-mode power amplifier (PA) is implemented in 40-nm bulk CMOS technology.
To boost the amplifier performance at millimeter-wave (mmWave) frequencies, a new …

A 60-GHz 32-way hybrid power combination power amplifier in 55-nm bulk CMOS

L Zhang, K Ma, H Fu - IEEE Transactions on Microwave Theory …, 2022 - ieeexplore.ieee.org
This article presents a high output power-band power amplifier (PA) with 32-way power
combining in 55-nm bulk CMOS. A new hybrid power combiner (HPC) is proposed and …

A 54–68 GHz power amplifier with improved linearity and efficiency in 40 nm CMOS

H Mosalam, W Xiao, X Gui, D Li… - IEEE Transactions on …, 2021 - ieeexplore.ieee.org
This brief presents a 54–68 GHz two-stage power amplifier (PA) with linearity and efficiency
enhancement in a 40 nm CMOS process. The first stage adopts a current reuse cascaded …

A K-Band High-Voltage Four-Way Series-Bias Cascode Power Amplifier in 0.13 m CMOS

JW Lee, BS Kim - IEEE Microwave and Wireless Components …, 2010 - ieeexplore.ieee.org
This letter reports a K-band high-voltage power amplifier delivering 100 mW output power in
CMOS technology. The amplifier used series-bias of four cascode power cells to increase …

A dual-mode wideband+ 17.7-dBm 60-GHz power amplifier in 65-nm CMOS

PM Farahabadi, K Moez - IEEE Transactions on Components …, 2017 - ieeexplore.ieee.org
This paper presents a 60-GHz power amplifier (PA) utilizing a novel technique to achieve
high efficiency at high output power levels. The proposed topology provides the capability of …

A 5.3-GHz 30.1-dBm fully integrated CMOS power amplifier with high-power built-in linearizer

JH Tsai - IEEE Microwave and Wireless Technology Letters, 2023 - ieeexplore.ieee.org
A 5.3-GHz watt-level fully integrated CMOS power amplifier (PA) with a high-power built-in
linearizer is presented in this letter. Utilizing a transformer (TF)-based 2-stage dual-radial …

A 60 GHz 19.6 dBm power amplifier with 18.3% PAE in 40 nm CMOS

CW Tseng, YJ Wang - IEEE Microwave and Wireless …, 2014 - ieeexplore.ieee.org
This letter reports a fully integrated 60 GHz power amplifier (PA) implemented in TSMC 40
nm CMOS technology. This PA is based on a three-stage two-way differential topology with …