FPGA architecture characterization for system level performance analysis

D Densmore, A Donlin… - Proceedings of the …, 2006 - ieeexplore.ieee.org
We present a modular and scalable approach for automatically extracting actual
performance information from a set of FPGA-based architecture topologies. This information …

Improving fpga design and evaluation productivity with a hardware performance monitoring infrastructure

AG Schmidt, R Sass - 2011 International Conference on …, 2011 - ieeexplore.ieee.org
Hardware design with FPGAs can be a daunting task, even for experienced engineers. Even
with sophisticated tools and improvements in high-level language to gates approaches, an …

Hwpmi: an extensible performance monitoring infrastructure for improving hardware design and productivity on fpgas

AG Schmidt, N Steiner, M French… - International Journal of …, 2012 - Wiley Online Library
Designing hardware cores for FPGAs can quickly become a complicated task, difficult even
for experienced engineers. With the addition of more sophisticated development tools and …

[PDF][PDF] Hybrid cpu/fpga performance models

A Parashar, M Adler, M Pellauer, J Emer - 3rd Workshop on Architectural …, 2008 - Citeseer
Pipeline parallelism is an inherent characteristic of structural performance models, which
makes them well-suited for mapping onto FPGA substrates. This observation, along with the …

Inter-FPGA routing environment for performance exploration of multi-FPGA systems

U Farooq, R Chotin-Avot, M Azeem… - Proceedings of the 27th …, 2016 - dl.acm.org
Multi-FPGA platforms are a popular choice today for complex system prototyping because
they offer high execution speed, low cost, and real world testing experience. However …

Exploiting FPGAs for technology-aware system-level evaluation of multi-core architectures

S Secchi, P Meloni, L Raffo - 2010 IEEE International …, 2010 - ieeexplore.ieee.org
The hardware-software co-development of modern complex MPSoC computing platforms
exposes to the designer a huge complexity, resulting from the combination of vastly different …

Balancing Accuracy and Evaluation Overhead in Simulation Point Selection

B Gottschall, SC de Santana… - 2023 IEEE International …, 2023 - ieeexplore.ieee.org
Simulators are the tool of choice when designing new computer architectures. While
software-based simulators are (relatively) easy to adapt to evaluate new architectural …

SoCLog: A real-time, automatically generated logging and profiling mechanism for FPGA-based Systems On Chip

I Parnassos, P Skrimponis, G Zindros… - … Conference on Field …, 2016 - ieeexplore.ieee.org
Recent advances in FPGA technology and the proliferation of High Level Synthesis (HLS)
tools makes it possible to implement complex System on Chip (SoC) designs that realize …

Using general-purpose programming languages for FPGA design

BL Hutchings, BE Nelson - Proceedings of the 37th Annual Design …, 2000 - dl.acm.org
General-purpose programming languages (GPL) are effective vehicles for FPGA design
because they are easy to use, extensible, widely available, and can be used to describe …

FPGA architecture design methodology

M Hutton - … Conference on Field Programmable Logic and …, 2006 - ieeexplore.ieee.org
Modern FPGAs are not just able to trade off speed and area, but features, cost, static power,
dynamic power, reliability and yield. This talk will discuss methodologies, metrics and …