Congestion has negative effects on network performance. In this paper, a novel congestion
control strategy is presented for networks-on-chip (NoC). For this purpose we introduce a …

Congestion in on-chip networks may cause many drawbacks in multiprocessor systems
including throughput reduction, increase in latency, and additional power consumption …

The network-on-chip (NoC) is a primary shared resource in a chip multiprocessor (CMP)
system. As core counts continue to increase and applications become increasingly data …

This paper proposes a novel congestion-aware Network-on-Chip (NoC) architecture that not
only enhances network transmission performance while maintaining a feasible …

Networks-on-Chip (NoC) architectures provide a scalable solution to on-chip communication
problem but the bandwidth offered by NoCs can be utilized efficiently only in presence of …

Today, due to the increasing demand for more and more complex applications in the
consumer electronic market segment, Systems-on-Chip consist of many processing …

Interconnection networks-on-chip (NOCs) are rapidly replacing other forms of interconnect in
chip multiprocessors and system-on-chip designs. Existing interconnection networks use …

In this work, we propose a new, accurate, and comprehensive analytical model for Network-
on-Chip (NoC) performance analysis. Given the application communication graph, the NoC …

This paper addresses communication optimisation for applications implemented on
networks-on-chip. The mapping of data packets to network links and the timing of the …

We propose (σ, ρ)-based flow regulation as a design instrument for System-on-Chip (SoC)
architects to control quality-of-service and achieve cost-effective communication, where σ …