This paper presents a 24GHz PLL design featuring programmable acquisition speed using
65nm CMOS. In a high frequency PLL, the locking time is easily affected by the variation of …

A fully integrated phase-locked loop (PLL) frequency synthesizer for WLAN applications is
designed in a 0.13-µm CMOS process. In order to make the loop bandwidth constant across …

This paper proposes a 60 GHz quadrature PLL frequency synthesizer that has a tuning
range capable of covering the whole band specified by the IEEE802. 15.3 c with exceptional …

This paper proposes a smart frequency presetting technique for fast lock-in LC-PLL
frequency synthesizer. The technique accurately presets the frequency of VCO with small …

A fully-differential quadrature PLL with common-mode noise immunity has been developed
by using a differentially controlled quadrature-VCO (Q-VCO) along with a differential charge …

A low-power high-speed frequency synthesizer in 65nm CMOS is presented. The design
features a novel architecture combining an LC quadrature VCO, two sample-and-holds, a …

In this paper, a fully integrated 24GHz integer-N PLL for a 60GHz wireless transceiver is
presented. A VCO with tail-feedback technique is used to improve the phase noise by …

In this work, a digitally assisted frequency locked loop is implemented using 32-nm CMOS
technology and acts as a 20-GHz frequency synthesizer. The frequency difference between …

Constructed from a current reused architecture for low power consumption, a cascode
topology of an LC VCO and a divide-by-4 prescaler is used in a PLL. In the prescaler, the …

A 20-GHz voltage-controlled oscillator (VCO) for phase-locked loop (PLL) synthesizer is
presented in this paper. The VCO and PLL synthesizer have been implemented using only …