Chip-package-interaction (CPI) induced BEoL (back-end-of-line) delamination has emerged
as a major reliability concern with the adoption of Cu/low-k as the mainstream BEoL …

As Cu bump is widely adopted in microelectronic IC product packages for broader scope of
applications throughout network communication and handheld device, it impacts on the …

Experimental and numerical studies were conducted to investigate Cu/low-k delamination
potentials of a flip-chip package assembly implemented with different underfills under an …

In the case of field programmable gate array (FPGA) chips, as the demand for higher speeds
and enhanced functionality increases, the size of the flip chip die grows accordingly to offer …

Ultra low-k (ULK, k= 2.4) dielectric has weaker mechanical properties than first generation
low-k films (k= 3.0). The introduction of ULK into advanced back end of lines (BEOL) …

Chip-packaging interaction is becoming a critical reliability issue for Cu/low-k chips during
assembly into a plastic flip-chip package. With the traditional TEOS interlevel dielectric being …

The reliability of Cu/low k interconnect structures using Cu pillar bumps was investigated in
this paper. First the characteristics related to electromigration (EM) of Cu pillars with Sn-Ag …

In this article, we review the reliability issues for plastic flip-chip packages, which have
become an enabling technology for future packaging development. The evolution of area …

A generalized plane strain condition is assumed for an edge interfacial crack between die
passivation and underfill on an organic substrate flip chip package. C4 solder bumps are …

As CMOS transistor scaling proceeds into the deep submicron regime, the number of
transistors on high performance, high density ICs is increasing to 45/spl sim/60 millions, in …